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set_case_analasys 0/1, in PT

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engr

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Hi All

by putting set_case_analysis 0/1 on any input ports,how PT disables that particular path?
can some pls explain little bit about set_case_analsys 0/1 {inpput port}, and its applications wiht elaborative explantion

Thanks and Regards
 

if you want to make the chip in some function and make an analysis for the timing, for example : pci slave status, you should make some pin or register in the chip become 0 or 1, now you need " set_case_analysis" to do so !
 

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    engr

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The same is when you want to do timing analysis in different mode, such as test mode and normal mode. When in test mode, you may use: set_case_analysis 1 [get_ports test_en]
 

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    engr

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my 2 cents,

to better understand the set_case_analysis commands execution assume a
2 input mux and a select line, but setting a value to 0 the first input of the mux gets activated and setting to 1 the second or other input gets activated in the mux, you image the same kind of scenario.

here you are using the same command in order the mask the timings which we are not interested off. and target the tool to concentrate on the timing paths of our interest

best regards,

chip design made easy
https://www.vlsichipdesign.com
 

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