14 bits accurate linear ramp generation

linear ramp ic

hi guys,

I would like to know the possible ways of generating ramp signal using 0.18um technology which is accurate upto 14 bits or more. the ramp should be linear and should range from 0 to 1.2 volts. What circuits and schematics can achieve this solution.

Thanks

linear ramp

If you just make a current, Vbg/R, and sum together 14 bits of switched binary currents into another R of same type, it will work.

However, I thought that super-duper layout technique could only get you 12 bits free. For 14 bits, they usually have to trim or use barrel-shifted LSB currents to spread the mismatch over the whole range. But that doesn't guarantee each bit is always accurate, it just spreads the mismatch.

What's the use of the ramp? Maybe a little varying mismatch won't bother it.

12 bit ramp with 0.1v gain error

the ramp generator is used for generating the calibration signal in pipeline
adc. The requirement is that the ramp can have an overall gain error perhaps upto 10% tolerance but the linearity should be maintained. So I was wondering what architecture we can use. Is it possible to generate the ramp using a switched capacitor integrator. Or if anyone has any other ideas please suggest. the area of the ramp should also not be too high.

ramp generation

A sigma-delta has guaranteed linearity, and can fit in a compact area. But it is not fast - can you afford lots of time for the calibration, or do you plan to do quick cal cycles every n conversions?

ramp bit linearity

well the ramp should reach its full scale range in about 16384*tclk seconds. so right now the adc is being designed for 100MHz but may increase in future. assuming 100MHz frequency of the clock we get about 163.84uS for the ramp to reach fullscale.

Can the sigma delta adc achieve this in such a short time. I plan to initially calibrate all of the adc parameters when it is switched on and than later on the ramp signal is introduced once every 14 clock cycles or so for calibration.

Thanks for your help

14 bit linear ramp signal

It may work for the first calibration, since 163uS is pretty long, but for calibaration every 14 clock cycles? Probably not.

Why do you think your calibration would only last 14 cycles before it was questionable?

One strategy may be to calibrate each of the bits one time on startup, and store those digital values in a table.

i mean the calibration constants are calculated and stored during the first run in a set of registers. The later ramp signals which i am sending into the adc are generated by a low speed clock and this is used to update the calibration constants slowly to take into account the temperature ageing etc. the initial clock that is used will have the same spped as the adc clock that is 100MHz. during the later updates the clock is divided internally to generate a slower clock so that the ramp steps are gnerated slowly over a much longer time. the clock in this case will be about 1/14th of the adc clock roughly.

Also I am not calibrating all the adc parameters once in every 14 clock cycles but rather each parameter is calibrated over a certain number of clock cycles.

Seems that the theme gets changing...

so back!

In CMOS:

Poly/Poly-Caps are the best and you will get about 10-12Bit matching with some area. The oxide quality und uniformity contributes here. Poly-Resistor ist between 9-11Bit. Diffusion and poly-grain gives little less performance than the oxide. Current matching is only 6-9Bit.

So how to make a 14bit reference DAC for the pipe ADC?

The only way is to combine a greater number of faily good matching device together. That is a resistor string DAC.

Sigma-Delta works only if there is either only two initial values or some kind of error randomisation. Both cases lead to high oversampling ratios. If you have to filter analog there is also filter settling.

A 14 bit reference dac will take up a lot of area. with such a huge number of resistors I think the power consumption is also be high. I was looking at a simpler implementation possibly a switched capacitor integrator. Sigma delta is also one possiblity as electronrancher has suggested. The main focus is lower area lower power consumption and linearity.
I didnt understand about the problems you mentioned with sigma delta requiring two intial values and error randomisation. Can you elaborate on this. And also do you think a switched capacitor integrator can be used in this case? If not why?

Thanks.

He means that if you use a 1-bit DAC in your sigma delta (with only 2 outputs from the modulator, 1 or 0) then you get guaranteed linearity. Those are the 2 initial values, 1 or 0.


If you use higher-order like 3-4 bit DAC you can run the sig-del at lower clock frequency (need less oversampling) but now you are no longer guaranteed linear. One way to avoid that is to barrel-shift a bunch of single-LSB's between all the bits of the DAC. Now if there are mismatches between LSB currents or something, they will be spread out (error randomization).

Ok, the linearity issue with a multibit-sigma-delta was discussed.

You do not need 2^1 devices either for current mode R2R DAC's with segmentation of for multi-resistor strings.

These two approaches work for a general DAC.

I still find the idea of a SC-integrator clever. If th opamp gain is high enough there is about 17bit linearity from the caps. Depends little on the process.

If that works for your calibration, its perfect. But there are some minor practical issues:

1. The SC requires then a cap scaling about 2^14. with adittional voltage scaling it is still critical.

2. Over longer times you have issues with leakage. 10pA/100pF=0.1V/s=100uV/ms.

3. The calibrations which I know aer mor interactive. So a calibration logic sets DAC values and observe the pipeline stages.

Thanks a lot for your replies. It really helped.