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DFT Scan insertion query

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anssprasad

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Hi,

when doing DFT scan insertion which of the following is true or is a better approach:

1. Up to three additional pins are required to implement this type of scan. Only the SCAN ENABLE pin must be dedicated; the remainder of the pins(scan in, scan out) can be shared with primary inputs and outputs.

2. Up to four additional pins are required to implement this type of scan. Only the TEST MODE pin must be dedicated; the remainder of the pins(scan en, scan in , scan out) can be shared with primary inputs and outputs.

Thanks
Prasad.
 

I think second approach is better. Since you'll need test_mode control to make the internal clock generating/distributing logic to switch to test_clock, and also make reset controllable.
 

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    anssprasad

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Another approach may be followed, wherein no top-level pins need to be dedicated for scan-enable.
The scan-enable can be configured to be from an internal register. Programming of this may be done serially using JTAG, wherein a new instruction may be defined so as to configure the internal register..
 

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    anssprasad

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nikhil.sudhakaran said:
Another approach may be followed, wherein no top-level pins need to be dedicated for scan-enable.
The scan-enable can be configured to be from an internal register. Programming of this may be done serially using JTAG, wherein a new instruction may be defined so as to configure the internal register..
Click to expand...

Yes y0u could, but then for at-speed coverage, you'll need to use Launch-on-Capture, which would increase the complexity of patterns somewhat....
 

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    anssprasad

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you can have only Test mode is a dedicated pin. rest all can be shared with functional pins at the top level.
 

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    anssprasad

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