clock uncertainity in synthesis

Hi All,

While doing the synthesis, i need to estimate the clock uncertainty and include in .sdc file , can anybody tell me how can i estimate the uncertainty(inputs are clock frequency)
Thanks

usually we set clock uncertainty to be 10% of the clock period,but sometimes it's over constrained,it depends on your clock provided.

Thanks LinXiaoling.

Can u pls give some idea on how to estimate max and min delays.

Thanks in advance

Hi eng,

clock uncertainty = clock jitter + clock skew

For Clock jitter value, you can get this value from your clock source.

FOr clock skew, you must have a target for your design.

So from this 2 value, you can set the value for clock uncertainty.

Hope this help

this depends on many factors (clock tree depth, jitter in the system, SI issues etc.)
usually a good rule of thumb is 10% but there is no one truth.
This number should be taken seriously - if you over constrain, your circuits will either become huge (due to low logic depth and a lot of necessary pipelining) on the other hand if you take a too short number, you might get into serious problems (e.g. setup issues - your clock will not arrive as expected on the capturing flop)

ND.

https://asicdigitaldesign.wordpress.com

the max delay and the min delay depend on the block or chip next to your design .if you have no idea about it,you have to do the timing budget,usually it takes 60% of clk period .but I dont recommend this method to constrain the design,you had better know well about other blocks,then u can constrain the design properly.
Hope it can help u, just for reference

hi
we generally go with the 10% of the clock period in the first pass , then after compleating the CTS part. we will be havin the idea about wht is the value can be used for the skew/uncertainity,,,and we redo the flow from synthesis again ,,,

Hi all,

While doing synthesis, we need to estimate the clock uncertainty and clock latency.
Thus, we include these into our SDC file (Pre layout STA).

After we layout the chip, then we need to verify the timing again (Post layout STA). Right?
Now, the question is do we still need to include the clock latency and uncertainty again in the SDC file or remove it during Post Layout STA checking?

I'm not a back-end or physical verification engineer.
Sorry if the question sound stupid.
I'm here to learn

Thanks.

The clock latency will be calculated by the STA tool in your postlayout runs, so it can be removed.
You'll need to keep in the clock uncertainty, to insure you have some amount of margin in the design.

there may be some source clock latencies in the post-layout designs, but clock with in the design should be propogated if not it wont be a valid STA.

Generally we keep uncertainity in final sta to give some margin in timing or to account for period/dcd jitter in the clock (generally tech node <65)

10% of clock period is a good choice

when you guys talk about clock latency and clock uncertainty, I would prefer these 2 values bind with a certain design phase, say, if you are in the early phase of the design, just start synthesis, no P&R yet, then there 2 values are only estimated one, you can put clock jitter + clock skew target for the uncertainty and put a estimated clock latency. however, as the work continues, after CTS, you can get more precise value for your clock latency (propagated) one, you can choose to re-synthesis your design with this value, as for the uncertainty, it must be reduced or modified, because after CTS, the tool propagated the clock and knows exactly the skew numbers, of course SI and OCV also taken care by the tool, so you must modify your sdc to adjust your clock uncertainty, if not, you can end up with a big design, because hold fixing put lots of delay buffers to the design since your uncertainty value is too big.