Mentor Graphic HDL FpgAdv

fpgadv

Is anyone out there expert in Mentor Graphic HDL Designer?

zpu fpga

Hi bruno,

I'm not an expert but I've used it before.
Post you questions or doubts and I'll try to help you out.

-no_mad

fpga zpu

Hi bruno,
what are your questions? i am dedicated in my work for the HDL Designer.

fpgadv 52

I'm currently using it.
I Think it's far better than Quartus and ISE but now I have trouble for using IP and Mega Function for example I want to use CAM/RAM mega function and also Ethernet and a soft core but I can't ...
is it possible to port it's project to other S.Ws?

opencores zpu

Hello no_mad,

Currently i'm learning a soft-core processor/IP-Core called ZPU. I've downloaded it from www.opencores.org. My task is to import all the ZPU Processor .vhd files in a library in Mentor HDL Designer.Now i need to implement it in FPGA Altera Cyclone.To establish a connection btw the soft-core processor and fpga, i need the wishbones interface. My question is should i includes the wishbone .vhd files in the same library , where i put my .vhd files of zpu processor?

Thx

Added after 9 minutes:

hello sadid,

i'm also still learning about a soft-core processor, called zpu, which i've downloaded from www.opencores.org.So at the moment i cant help you.

mentory graphics hdl designer hdl import wizard

If you want to implement a project in @ltera's FPGA, you'd better use qu(at)tus, it will save a lot of problems.

hdl to graphic

hello craftor,
it is a comparative issue

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

entity hello_world is
port (
clk : in std_logic;
-- reset : in std_logic;
led : out std_logic
);


end entity hello_world;

--
architecture rtl of hello_world is
constant CLK_FREQ : integer := 20000000;--20000000
constant BLINK_FREQ : integer := 1;
constant CNT_MAX : integer := CLK_FREQ/BLINK_FREQ/2-1;

signal cnt : unsigned(24 downto 0);
signal blink : std_logic;


begin
process(clk)
begin
-- if reset <='1' then
-- blink <='0';

if rising_edge(clk) then
if cnt=CNT_MAX then
cnt <= (others => '0');
blink <= not blink;
else
cnt <= cnt + 1;
end if;
end if;

end process;

led <= blink;

end architecture rtl;


I tried to run this programm to blink led in both quartus and fpgadvantage from mentor, but it was only successfull in quartus..anyone has idea about this??

mentor only give you edf netlist, later then you have create another project in quartus, use this edf file as top design and that is it