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The "gate count" of a chip is a largely meaningless metric that has been almost abandond by the industry. Sometimes it is used in marketing materials because its meaning is so vague that you can hide the true details of your chip while still quoting a number.
The most accurate and meaningful metric for density is the number of transistors on the chip area. This is used to evaluate the processing technology that was required to create the chip.
But when talking about design effort, the number of placeable instances or the % utilization (cell area/ core area) is the more popular and meaningful metric. The reason is that for a place-and-route tools a RAM, for example, is just one object to place. A FF is one object, a PLL is one object. It doesn't matter that the RAM has a million transistors, nobody designs digital chips at the transistor level.
Natg9's idea that a gate contains exactly 4 transistors and that there is a strict equivalence between gate count and transistor count may be true in some academic text book, but is never applied that way in reality. Gate count is a deliberately vague number that everybody interprets differently. It had more validity in the early days of ASIC design, but now - if it is used at all - it is used to conceal rather than reveal information.
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