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Hi,
Using fifos is the best way out. The answer suggested by vipulsinha isn't going to work. A simple binary counter which increments the count by 1, when mapped to gray code, shows the hamming distance of 1 between 2 successive counts. While here if we map the data to gray code, it is almost certain that the data will not behave like a counter, so the o/p gray code will not have a hamming distance of 1, and hence this method will not work.
Kr,
avi
Theres more to it.
If you want to transfer a single bit level signal use double ranked FFs. If the width of the signal is less than the clk you will have to add a pulse synchronizer
For data buses, use a mux synchronizer or FIFO. If latency is allowed a mux synchronizer is acceptable but if your data bus changes every clk, use a FIFO.
The Gray to binary and B2G "HAS" to be used for FIFO pointers crossing clock domains, since at pointer rollver (0111 to 1000), we need a safe transition. It is something like this B2G -> double_ranked_ff -> G2B
HTH,
Beo
In reply to Avi I have to make a point as FIFOs are used to match the data rate across the clock domain when we use async FIFOs. But in the case when the data rate is dame and clck phase is different then we have to use b2g converter and once the gray code is sucessfully obtaimed in the other clock domain then do g2b
each solution has it's own limitations. using FIFOs is usually more complicated and just bigger.
if speed is not an issue, you should do a simple 4 phase (or 2 phase) handshake between a request and acknowledge signals and then transfer the entire bus over.
look at chapter 7 of the following book: https://www.cmosvlsi.com/
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