Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

What to take care of when doing floorplan?

Status
Not open for further replies.
N

neal

Newbie level 2
Newbie level 2
Joined
Jan 12, 2004
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
22
floorplan

Hi everyone,
when we do floorplan, There are so many things we should take care, especially for SOC design. But who can collect the information as many as possible into one file . I think that is very usesul for digital enginner. Can you post what you know about the FP .
 

Re: floorplan

Hi,

The principle behind SOC floorplan is to prevent the interference between different blocks ,especially the analog blocks. So how to reduce the noise
on chip is the primary issue. Here are two useful articles for your reference .

Hope it helps : )
 
Re: floorplan

yes ,hehe. 3x.
But when we do full chip floorplan ,we should consider the congestion, the noise between the analog module and digital module, chipsize , power, performance. We should do it according to the specification.
How to minmize the congestion problem when we want to get a better performance ? we may use EDA tools .But for floorpan, there are still many thing we should do mannully.
During the curse of mannul work, I think the problem what we should take care is even important. Can you show us in detail?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top