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How to get around hold violation in Silicon..??

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vinun_7

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Assuming u have a silicon in hand, if u have a setup violation, u can still get around it by lowering the frequency. But if u have a hold violation is it possible to get across it at least to test the functionality of the chip. Is there any way/method for it...?
 

Thy working on different temperatures, with your fingers crossed. There is not much you can do abt it
Avi
 

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    vinun_7

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Oh.. okay.. so that varies the delay is it...?
 

hi Nir Dahan
i think the qn is after chip is realiszed on silicon ,, thn u have some hold violation,,,,,
yep,, i too listend some time back that the change in temp ,,, increase in temp can increase the delay and can help in removing hold violation
 

try to run the patterns in the SS conditions...that is " higher temperature and low voltages".. this will imporve the hold.
 

Hi,

If u have inserted some spare cells in ur design, using eco (engg. chage order) u cn use them as a hold fixing buffers with some changes in final netlist and accordingly the routing. It requires a small chage not a complete respin.

It may help you.

Thanks.

HAK.
 

You could also try a FIB if you are extremely desperate and it is just one violation you need to fix
 

Take the product on silicon at a higher temperature and find the highest temperature at which it is properly functional. You can also lower down the operating voltage and find out the maximum value of voltage at which the design functions properly.

Ultimately you are losing some temp and voltage range for this hold violation

Hi jbeniston

What do you mean by FIB?
 

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