engr
Member level 3
Hi All
I am looking for some help regarding synthesis, i am using the DC tool.
i need to set the constrains, DRC constrains are by set in the tech lib we use.
I need to understand how can i set the optimization constrains( input delay, output delay, and min and max delay,clock uncertinity and latency and false path and multi cycle paths), the inputs that i have for this is , clock frequency of the chip.
Could you pls provide any doc which explains in elaborate with examples about these.
I read DC user guide, it explains syntax of the command to set the constrains, but it doest explain, how we can estimate those constraints
Thanks in advance
I am looking for some help regarding synthesis, i am using the DC tool.
i need to set the constrains, DRC constrains are by set in the tech lib we use.
I need to understand how can i set the optimization constrains( input delay, output delay, and min and max delay,clock uncertinity and latency and false path and multi cycle paths), the inputs that i have for this is , clock frequency of the chip.
Could you pls provide any doc which explains in elaborate with examples about these.
I read DC user guide, it explains syntax of the command to set the constrains, but it doest explain, how we can estimate those constraints
Thanks in advance