Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Help require on verilog

Status
Not open for further replies.
PekingBoy

PekingBoy

Newbie level 4
Newbie level 4
Joined
Jul 3, 2008
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,313
Hi,i got a verilog file as the follow,

...
case(f4Cnt)
'd0:
begin
a <= b+1;
f4Cnt <= f4Cnt+1;
end
'd1:
begin
a <= b+1;
f4Cnt <= f4Cnt+1;
end
'd2,
'd3,
'd4,
'd5:
begin
a <= c+1;
f4Cnt <= f4Cnt+1;
end
default:
begin
a <= 'd0;
f4Cnt <= 'd0;
end
endcase
...
The question is what the operation will be in state 'd2,'d3,'d4?

Thanks in advance.
 

case(f4Cnt)
'd0:
begin
a <= b+1;
f4Cnt <= f4Cnt+1;
end
'd1:
begin
a <= b+1;
f4Cnt <= f4Cnt+1;
end
'd2,
'd3,
'd4,
'd5:
begin
a <= c+1;
f4Cnt <= f4Cnt+1;
end
default:
begin
a <= 'd0;
f4Cnt <= 'd0;
end
endcase
...
The question is what the operation will be in state 'd2,'d3,'d4?

After `d1 state, then the state will be in state `d2 -> `d3 -> `d4.

Am i answer your questioN?
 

Hi ,

I think there is no operation done . U are just adding 3 cycles of delay
 

...
case(f4Cnt)
'd0:
begin
a <= b+1;
f4Cnt <= f4Cnt+1;
end
'd1:
begin
a <= b+1;
f4Cnt <= f4Cnt+1;
end
'd2,
'd3,
'd4,
'd5:
begin
a <= c+1;
f4Cnt <= f4Cnt+1;
end
default:
begin
a <= 'd0;
f4Cnt <= 'd0;
end
endcase
...
The question is what the operation will be in state 'd2,'d3,'d4?

Be a little more Precise.

At the moment it looks like a 3 cycle delay. Nothing else
 

That means the state of 'd2 'd3 'd4 'd5 are the same state.
 

    PekingBoy

    PekingBoy

    Points: 2
    Helpful Answer Positive Rating
icelucent said:
That means the state of 'd2 'd3 'd4 'd5 are the same state.
Click to expand...

Thank you,everyone.
I think icelucent is right.
 

The logic behaviour can be unequivocally concluded from Verilog language specification. The 2 to 5 are not the same state, in so far as they are cycled sequentially, they are just handled by the same case expression. This doesn't necessarily mean much for the synthesis tool, that can be expected to treat each case independently when minimizing the logic.

The unsized 'd2 constant can be written simply 2, by the way.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top