vamsi_addagada
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clock uncertainty
what is clock latency and clock uncertainty plz tell me
what is clock latency and clock uncertainty plz tell me
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right, and for detailed information, refer to MarcS's reply. It is very detail and professional.binglingxiao said:The clock uncertainty contains two parts: skew and jitter.
Clock jitter could also be defined as the crosstalk effect on the clock nets. Since a clock tree is used, different clock branches can have different crosstalk and therefore different jitter. Therefore this effect needs to be modeled or uncertainty introduced to add enough margin.
How is the clock jitter handled in the design? Do we need to add extra uncertainty to fix it, or is it handled by an increased on chip variation setting?
Hey Marcs,
If we are taking on chip variation as a factor for the clock uncertainity then why
is there OCV margin set seperately while timing the design.????????
Thanks
Ahtesham
I wonder whether it is 50 ps or 100ps. BecauseFor example, a 1 ns clock with a 100 ps clock uncertainty means that the next clock tick will arrive in 1 ns plus or minus 50 ps.
Marcs, thanks for your great explanation.
I still have some question.
1.
I wonder whether it is 50 ps or 100ps. Because
creat_clock -period 1 [get_ports CLK]
set_clock_uncertainty -setup 0.1 [get_ports CLK]
Then the max allowable delay for reg2reg pah is (1-0.1-setup in lib) but not (1-0.05-setup in lib)