equivalent function in Verilog for VHDL 'LENGTH function?

verilog log function

Hi,
Is there a way or an equivalent command in Verilog which does the same thing as the 'LENGTH function in VHDL? If I am correct, the syntax of

will return the bit size of the signal "Data", which is what I would like to do.

thanks

equivalent of (others => 0) in verilog

No, Verilog-2001 doesn't have any equivalents for many VHDL attributes ('size, 'left, 'right, 'high, 'low, etc.)

...but that's where Systemverilog 1800-2005 comes in...

Systemverilog has a direct-equivalent for most of the VHDL-attributes/properties (including 'length). SV is still missing some, but it's a vast vast improvement over legacy Verilog.

length in vhdl

boardlanguage said:

No, Verilog-2001 doesn't have any equivalents for many VHDL attributes ('size, 'left, 'right, 'high, 'low, etc.)

...but that's where Systemverilog 1800-2005 comes in...

Code:

$size(Data)

Systemverilog has a direct-equivalent for most of the VHDL-attributes/properties (including 'length). SV is still missing some, but it's a vast vast improvement over legacy Verilog.

Click to expand...

thanks!

Can you recommend a good book for learning more about System Verilog commands?

However.. I did a quick check at Amazon, and from that I gather that System Verilog is for testbenches ? I need this to create a functional/behavioral model. Will this still be synthesizable?

length vhdl

Because it's new, Systemverilog is not as widely supported as VHDL or Verilog-2001.

You're right -- at the moment, it's mostly used for testbench/verification. But there is a synthesizeable subset of Systemverilog, so it can be used for new designs. Altera Quartus-II 8.0, Synopsys Design Compiler, Cadence RTL Compiler can synthesize Systemverilog RTL. (I think other tools like Synplicity can do it, too, but Design Compiler is probably the best at the moment.)

An older PDF version of the Systemverilog standard (3.1a) is available from:
**broken link removed**

As for books, there have been books posted in this forum and others -- just do a search and they'll come up.

Anyway ... if you must stay with Verilog, then unfortunately there's no direct equivalent for 'LENGTH. You can sort of work around that by using a parameter (it works just like a VHDL generic)