One question on class-d audio design

Hi,
I have a question on the class-d audio design. In the silicon test, I found the output will be shut down periodicly when the supply voltage is high or the input signal level is high.

After FIB, I found the bounce of the digital VDD is high and it falsely triggered the auxiliary overheat protection block and then it output wrong alarm signal. So, output power stage is wrongly shutted down.

What I am confused is, in the system simulations, the di/dt noise is simulated and the bording wire of package is also counted into the L*di/dt noise evaluations. But obviously, the bounce is larger than the simulation. I wonder why the big discrepancy between the simulation and actual silicon test results? Is there anything I missed in the designing?

PLs. shed some light on it.

Thanks a lot!

What's inductance did you use for bonding wire in your simulation?

leo_o2 said:

What's inductance did you use for bonding wire in your simulation?

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The package is MSOP-8, I figured the inductance is ~2nH. And I think it should be enough.

Any comments?

Regards

I think the inductor of banding wire is larger than 2nH, perhaps.
You can find it in the PDF document of banding wire.
We use 5~8nH usually.

lylnk said:

I think the inductor of banding wire is larger than 2nH, perhaps.
You can find it in the PDF document of banding wire.
We use 5~8nH usually.

Click to expand...

Hello, lylnk,
What vakue you used for the parasitic resistor of bording induactor?

Thanks

We use 100mohm sometimes.
I think the resistance on the BGA substrate is large.