Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

High Impedance in Verilog-A

Status
Not open for further replies.
B

bajji_boy

Newbie
Newbie level 3
Joined
Oct 13, 2006
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,306
Hi everyone

I was wondering if there was a way to model a floating node in verilog-a. I was actually working on a simple model for a switch (including its on-resistance). What is wish to do is to 'float' the output node when the switch is off...

Cheers
Nihit
 

You can do two things, either a large Roff or open switch. I prefer the first for simulation converging.

So when you have

V(in,out) <+ I(in,out) * Ron;

in the on state, you would have either

V(in,out) <+ I(in,out) * Roff;

or

I(in,out) <+ 0;

Hope this helps.
 

    B

    bajji_boy

    Points: 2
    Helpful Answer Positive Rating
Thanks for the response solidstate

I tried the latter, I(in, out) <+ 0, but as you guessed, it gave me convergence issues since V(out) was connected in a feedback loop.

I will be probably try the first model and get back to you...

Cheers
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top