missbirdie
Member level 1
duty cycle vhdl
How can I implement in VHDL a 10% Duty cycle clock from the 50 MHz clock in spartan 3 ??
How can I implement in VHDL a 10% Duty cycle clock from the 50 MHz clock in spartan 3 ??
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module top (clk, clkout);
input clk; // synthesis attribute PERIOD clk "50 MHz";
reg signed [9:0] count=0;
output clkout;
BUFG u1 (.I(count[9]), .O(clkout)); // clock buffer
always @ (posedge clk)
count <= count == 449 ? -50 : count + 1;
endmodule