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DRC ERROR "minimum density"

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sykab

sykab

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nofill layer not in lsw

Can anyone explain me what's the meaning of the error "Minimum MET1 density= 30%"?
And how can I solve this problem?

Thanks
 

density rules drc

Density metal (filling) must be more 30% (on whole chip)
Solution: skip, ignore
 

    sykab

    sykab

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minimum density design rule check

You can generate a fill at the end of the design which will add metal wherever it can, (use nofill to to stop it filling areas you don't want covered oin metal.
 

    sykab

    sykab

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Hi,
Minimum density error will go off once you do the dummy fill.

So you dont want to worry about it.

Regards,
Analayout.
 

    sykab

    sykab

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how can we solve that DRC error. i didn't understand the density of metal. how can we improve density of matal.
pls clarify my doubt.
 

    sykab

    sykab

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hi,
According to the process you are following ,and the technology u r using .There generally fab rules which states that for certain area exceeding ,depending on metal layers allowed ,there rules which constrain the density of metals allowed.so to avoid we use dummy metal fill pattern ,generally this is done at top level only.
Regards,
Roy
 

    sykab

    sykab

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actually this is the DFM requirement. it is especially important for the YIELD.

you can fill dummy metel or widen your power bus to fix it.
 

    sykab

    sykab

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some foundry fix such errors in EB making.
 

    sykab

    sykab

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Loktik_Vitalij said:
Density metal (filling) must be more 30% (on whole chip)
Solution: skip, ignore
Click to expand...

i suggest add dummy metal
on each square area in 90nm technology
on whole chip in 130nm above
 

    sykab

    sykab

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What is the exact name of this "NOFILL" layer, which prevents dummy structures on places that I don't want to be filled?
 

we call it metal dummy layer. there is an specific rule about it. check your design rule.
 

when is drawn subcircuit she is not filled additional layers . this error skip. when whole crystal ready, then script are filled empty area. and this not only metals, all depend on technological process. it may be ACTIVE, DIFF, .....
 

Typically, the mim metal density rules will have to do process control for metal pattern etch. In this case, if the metal pattern density doesn't match criteria 0f 30%, there is the risk some metal inside the circuit somewhere else will be over-etched, let's say the possibility might happen at the area where the metal density is lower in respect to other area in the circuit.
Solution will be adding the dummy metal pattern in the metal layer which violated the rule.
If ignoring the rule, there would be yield maintenance issue depending on the process control capability of the fab you use.
 

you can add some dummy layer at the spare area.
or just ignore it.

Our analog layout is small, we ignore this warning.
 

    sykab

    sykab

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malizevzek said:
What is the exact name of this "NOFILL" layer, which prevents dummy structures on places that I don't want to be filled?
Click to expand...

The exact name of the layer "NOFILL" is NOFILL.

You may need to go into the edit menu of LSW and then choose set valid layers if it is missing from your list.
 

As long as its not the full chip layout that you are doing, you can safely ignore the error for the time being..
Metal Density errors are for DFM which are generally taken care of in the top layout by putting dummies.
 

    sykab

    sykab

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you can ignore it,for the charge discharging the fabs put the metal
 

    sykab

    sykab

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-->The exact name of the layer "NOFILL" is NOFILL.

This depends on the design kit you are using. if you can't find the layer "NOFILL", you should probably go and check your design rules and/or PDK documentation. It'll tell you what layer name corresponds to this "NOFILL" layer.
 

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