yangbay81983
Newbie level 4
Hi,
when we make a sub-ip specification for DRAM controller before our RTL design, how to evaluate and add constraints on output ports who will be connected to SDRAM, Thanks! for example, set_load=?
Another question is the result of synthesis of AHB bus. Does it contain only Arbiter and Decoder? Once again, Thanks!
Yang
when we make a sub-ip specification for DRAM controller before our RTL design, how to evaluate and add constraints on output ports who will be connected to SDRAM, Thanks! for example, set_load=?
Another question is the result of synthesis of AHB bus. Does it contain only Arbiter and Decoder? Once again, Thanks!
Yang