What's exactly meant by technology shrinking?

Hi,

What's exactly meant by technology shrinking?
Is it something the like metal pitch or the gate length?

for eg, 65nm means....the minimun matla pitch is .065u or the min gate length is .065u?

Plz clarify..

Thanks in advance..

Re: Technology shrinking

that's the length of gate and it represents the characteristic of technology.

Re: Technology shrinking

Hope I have understood what u have asked.

To provide more die or sample die on a wafer, some foundry provide the shrinking service,for example: you chip is 5mm*5mm after layout a design, if the foundry provide the 0.9 shrink service, then in manufacture, the chip will be 4.5mm*4.5mm

the shrink manner is variety, some foundry reversve the channel L and channel W value,only shrink the wire spacing contact size,etc; some foundry shrink all the demension.

we can think that, if a tr shrink the W and L with the same ratio, the W/L is not changed, though its characteristics has a little change; the W and L of the resistor shrink with the same ratio, the res value will not change; the cap value will change after change, so if we know the chip will shrink before we do layout, we need to account for this.

Technology shrinking

Thank you jiangxb and llbaobao ...

Shrinking down the technology frm 65nm to 45 nm means only the length of the gate is shrinking or any other charachetristics are also changing??

llbaobao,
could you please explain me about shrink service?

And if we already layed out a design in accordance with the die area of 5mm*5mm, again the foundary has the provision to shrink the die area? If so, how can we accomidate the layout of 5mm*5mm into the shrinked area?

Is that means we need to relayout everything with the changed w/l values?

Re: Technology shrinking

when the characteristic length is scaled down from 65nm to 45nm, it indicates the channel length decreases. accordingly some other parameters such as oxide thickness, metal width, impurity concentration, etc. also change.

Re: Technology shrinking

We should know that, the Vth value is W and L dependent.
If the W and L larger than a certain value, then the dependent decrease.
then, if only L changed to more small, then the Vth must be changed to some extent.

We do not need to relayout a design, if we shrink the layout.
The foundry just use EDA tools or pure optical method to fullfill the shrink.
As I have said, we must know if we will shrink the layout before we begin the layout, for the capacitence vaule will be changed after shrink due to area decrease.
Then, if we know the shrink value, for example 0.9, we need to enlarge the capacitance area to be about 1.111(for 1.111*0.9=1) .

As to shrink service, it is just what I called it. I do not know how foundry called this. But many foundry have ability to provide such service.

Technology shrinking

what you talk is for the digital circuit design?
is it fit for analog circuit design shrink?
if not , can you give some advisize? or give some material?