systemverilog interview questions post ur answers for these

system verilog interview questions

Qi1)What is callback ?

(Qi2)What is factory pattern ?

(Qi3)Explain the difference between data types logic and reg and wire .

(Qi4)What is the need of clocking blocks ?

(Qi5)What are the ways to avoid race condition between testbench and RTL using SystemVerilog?

(Qi6)Explain Event regions in SV.

(Qi7)What are the types of coverages available in SV ?

(Qi8)What is OOPS?

(Qi9)What is inheritance and polymorphism?

(Qi10)What is the need of virtual interfaces ?

(Qi11)Explain about the virtual task and methods .

(Qi12)What is the use of the abstract class?

(Qi13)What is the difference between mailbox and queue?

(Qi14)What data structure you used to build scoreboard?

(Qi15)What are the advantages of linkedlist over the queue ?

(Qi16)How parallel case and full cases problems are avoided in SV ?

(Qi17)What is the difference between pure function and cordinary function ?

(Qi18)What is the difference between $random and $urandom?

(Qi19)What is scope randomization ?

(Qi20)List the predefined randomization methods.

(Qi21)What is the dfference between always_combo and always@(*)c?

(Qi22)What is the use of packagess?

(Qi23)What is the use of $cast?

(Qi24)How to call the task which is defined in parent object into derived class ?

(Qi25)What is the difference between rand and randc?

(Qi26)What is $root?

(Qi27)What is $unit?

(Qi28)What are bi-directional constraints?

(Qi29)What is solve...before constraint ?

(Qi30)Without using randomize method or rand,generate an array of unique values?

(Qi31)Explain about pass by ref and pass by value?

(Qi32)What is the difference between
bit[7:0] sig_1;
byte sig_2;

(Qi33)What is the difference between program block and module ?

(Qi34)What is final block ?

(Qi35)How to implement always block logic in program block ?

(Qi36)What is the difference between fork/joins, fork/join_none fork/join_any ?

(Qi37)What is the use of modports ?

(Qi38)Write a clock generator without using always block.

(Qi39)What is forward referencing and how to avoid this problem?

(Qi40)What is circular dependency and how to avoid this problem ?

(Qi41)What is cross coverage ?

(Qi42)Describe the difference between Code Coverage and Functional Coverage Which is more important and Why we need them

(Qi43)How to kill a process in fork/join?

(Qi44)Difference between Associative array and Dynamic array ?

(Qi45)Difference b/wProcedural and Concarent Assertions?

(Qi46)What are the advantages of SystemVerilog DPI?

(Qi47)how to randomize dynamic arrays of objects?

(Qi48)What is randsequence and what is its use?

(Qi49)What is bin?

(Qi50)
Initial
wait_order(a,b,c);

Which from below initial process will cause that above wait order will pass.
a)
ig initial begin
#1;
->a;
->b;
->c;
end

b)
initial begin
#1;
->a;
end
always @a->b;
always@b-> c;

c)

initial begin
#1;
->a;
#0 ->b;
->>c;
end

d)

initial begin
#1 ->a;
#1 ->b;
#1 ->c;
end


(Qi51)Why always block is not allowed in program block?

(Qi52)Which is best to use to model transaction? Struct or class ?

(Qi53)How SV is more random stable then Verilog?

(Qi54)Difference between assert and expect statements?

(Qi55)How to add a new processs with out disturbing the random number generator state ?

(Qi56)What is the need of alias in SV?

(Qi57)What would be the output of the following code and how to avoid it?
for(int i=0; i<N;i++)begin
fork
int j = i;
begin
#10 $display(" value is 0",j);
end
join_none
end

always N,By using automatic Key word, This problem can be avoided .
fori(int i=0; i<N;i++)begin
fork
automatic int j =i;
begin
#10 $display(" value is 0",j);
end
join_none
end

(Qi58)Is it possible for functions to return a array( memory) ?

(Qi59) How to check weather randomization is ssuccessful or not?

(Qi60)Do we need to call super.new() when extending a class ? What happens if we don't call?

(Qi61)Equivalent construct to |-> 1?
Ans:=>

(Qi62)What is the need to implement explicitly a copy() method inside a transaction , when we can simple assign one object to other ?

(Qi63)How different is the implementation of a struct can union in SV.

(Qi64)What is "this"?

(Qi65)What is tagged union ?

(Qi66)What is "scope resolution operator"?


(Qi67)What is the difference between Verilog Parameterized Macros and SystemVerilog Parameterized Macros?


(Qi68)What is the difference between
logic data_1;
var logic data_2;
wire logic data_3j;
bit data_4;
var bit data_5;

(Qi69)What is the difference between bits and logic?

(Qi70)Write a Statemechine in SV styles.

(Qi71)What is the difference between $rose and posedgec?

(Qi72)What is advantage of program block over clockcblock w.r.t race condition?

(Qi73)How to avoid the race condition between programblock ?

(Qi74)What is the difference between assumes and assert?

(Qi75)What is coverage driven verification?

(Qi76)What is layered architecture ?

(Qi77)What are the simulation phases in your verification environment?

(Qi78)How to pick a element which is in queue from random index?

(Qi79)What data structure is used to store data in your environment and why ?

(Qi80)What is casting? Explain about the various types of casting available in SV.

(Qi81)How to importuall the items declared inside a package ?

(Qi82)Explain how the timescale unit and precision are taken when a module does not have any timescalerdeclaration in RTL?

(Qi83)What is streaming operator and what is its use?

(Qi84)What are void functions ?

(Qi85)How to make sure that a function argument passed has ref is not changed by the function?

(Qi86)What is the use of "extern"?

(Qi87)What is the difference between initial block and final block?
Ans:

You can't schedule an event or have delays in final block.


(Qi88)How to check weather a handles is holding object or not ?

(Qi89)How to disable multiple threads which are spawned by fork...join

system verilog interview question

I think if you have learnt system verilog .... then most of questions can be answered ......... You can refer to book Verification using System verilog by chris Spear.

systemverilog interview questions

I don't understand. Is this an interview-test, that the applicant is supposed to finish on-site? Or is it a 'take-me-home' test, that you submit online?

These questions are pretty basic, but the test's comprehensiveness makes me think it's aimed at experienced systemverilog users. A beginner isn't going to remember everything about systemverilog in one sitting -- that only comes with real-world experience.

interview questions systemverilog

Yes i completely agree with boardlanguage ...... if you know system verilog then only you can give the answers of most of them.

faq on system verilog

Yaa man these are basic questions in systemverilog . If u know some of the questions u can post rite so that it can helpful for others .. i am trying to form a group of people whose working on systemverilog ..so that it can helpful for most of the people who started learning systemverilog and for experienced people also..

regards
mallik

Can I not declare variables as rand or randc if the variables are inside a function within a class?/

ex:
class example
---
----
function void test();
rand integer x;
endfunction
endclass

The above code gives me error saying rand cannot be used in this context. Is it because I cannot declare private or protected variables(variables inside the function test) as rand?

please reply

Hi,
No you cant do it .Its illegal. Class consists of data and routines to manipulate the data. Function and tasks are routines to manipulate the data .
So Declare rand integer x before any routines .

Thanks,
Sunny

shwetha100 said:

Can I not declare variables as rand or randc if the variables are inside a function within a class?/

ex:
class example
---
----
function void test();
rand integer x;
endfunction
endclass

The above code gives me error saying rand cannot be used in this context. Is it because I cannot declare private or protected variables(variables inside the function test) as rand?

please reply

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