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First, take note the 50Ohm matching.
Sencend, note the GND which should be very good GND. Usually, the GND should be a whole layer.
Third, note the traces balance and match if needed.
Forth, GOOD power supply. It is very important especially for the noise sensitive circuit.
If you're looking for a check list, here's a basic one:
1) Make sure you know the dielectric constant of the board. If you use FR4, and are really high frequency (say 4 GHz) or higher, you may need to design for losses along traces. This is because the dielectric constant of FR4 is only guaranteed to be in a range of values, and changes over time.
2) Keep all traces less than 1/10 of a wavelength.
3) Get an online calculator to tell you what width your traces should be for your frequency (impedance matching).
4) Always try to have one plane in your board GND, and another plane for power.
5) Always get your decoupling capacitors as close to the power pins on chips as possible. This may require using small components such as 402's if the frequency is high enough.
6) You'll also want to make sure you use the smallest components available for the power levels you require.
7) For high frequency traces, surround them with via's that short to the ground plane. These do not touch the trace, they just surround it.
This list is not complete, it is just a few tricks I have learned from designing a 4.6115 GHz PLL. As always, an expert should be consulted before trying anything dangerous and my word should not be taken as the final truth.
RF layout is kind of art. Designer spends years until collect good experience. All recommendations above are true and helpful, but definitely they are not a full list. I want to tell about one important point that many young engineers often overlook. This is the length of the trace and it effect on RF circuit. Often RF engineers consider that trace should be shorter that 1/20 or 1/10 of wave length. This is not always true. Any length of the trace is changing the reactive part of impedance connected to one of the end, therefore the opposite end may see totally different impedance. Here is just one example from the real life. About 2000 I was asked to investigate problems with newly designed VCO. It was suggested generating RF signal around 527 +/-30 MHz which is not very high frequency for RF design. Varactor has capacitance of 7.5pF (for central frequency of 527 MHz) and was installed at the distance about 5 mm from the chip and as result chip saw capacitance of 19.3 pF! This is almost three times more than designer expected. On the board with dielectric constant about 3 we get wave length for 527 MHz roughly 330 mm. 5 mm is about 0.015 from 330 mm. Trace length that is just 1.5% of wavelength multiply capacitance for almost three times! You can easily check all these numbers with RF simulation program or with simple equations. This example clearly shows how it is important to keep all connections as short as it possible, not just 1/10 of wavelength. Some RF components like baluns, transformers (especially broadband) are very sensitive to reactive part of impedance and require short connecting traces. In RF design any component, even soldering point, must be considered with they intrinsic parasitic elements and their effect must be accounted. Wire is not just a wire and resistor is not just resistor, they are complex elements.
Find attached a document from HENRY OTT CONSULTANTS & mentorpaper_32889.pdf. It will give some idea.
PCB DESIGN GUIDELINES
Guidelines for the design and layout of high-speed digital logic PCBs.
• Give a lot of consideration to component placement and orientation.
• Avoid overlapping clock harmonics. Make a harmonic table for each clock.
• Clock signal loop area must be kept as small as possible. Get paranoid about clocks!
• Use multilayer boards with power & ground planes whenever possible.
• All high frequency signal traces must be on layers adjacent to a plane.
• Keep signal layers as close to the adjacent plane layer as possible (< 10 mils).
• Above 25 MHz PCB's should have two (or more) ground planes.
• When power & ground planes are on adjacent layers, the power plane should be recessed from the
edge of the ground plane by a distance equal to 20 times the spacing between the planes.
• Bury clock signals between power & ground planes whenever possible.
• Avoid slots in the ground plane. Also applies to the power plane.
• If a segmented power plane is necessary, signal traces must not be routed over the slots.
• Filter (series terminate) the output of clock drivers to slow down their rise/fall times and to reduce
ringing (typically 33 to 70 ohms).
• Place the clocks & high-speed circuitry as far away from the I/O area as possible.
• Use a minimum of two equal value decoupling capacitors on DIP packages, four on square packages.
On high frequency/high power/noisy IC's many more capacitors may be necessary.
• Consider using embedded capacitance PCB structures for decoupling on h-f boards (>50 MHz)
• Use impedance-controlled PCB layout techniques (with proper terminations) where necessary
• On impedance-controlled PCBs, do not transition the signal from one layer to another unless both
layers are referenced to the same plane.
• On non impedance-controlled PCBs, when a clock transitions from one layer to another & the layers
are referenced to different planes add a transfer via or capacitor between the planes.
• All traces whose length (in inches) is equal to or greater than the signal rise/fall time (in
nanoseconds) must have provision for a series-terminating resistor (typically 33 ohms).
• Simulate all nets whose length (in inches) is equal to or greater than the signal rise/fall time (in ns)
• Connect logic ground to the chassis (with a very low Z connection) in the I/O area. This is crucial!
• Provide for an additional ground to chassis connection at the clock/oscillator location.
• Additional ground to chassis connections may also be required.
• Daughter boards (with h-f, noisy devices and/or external cables) must be properly grounded to the
motherboard and/or chassis (do not rely on the ground pins in the connector to provide this ground).
• Provide C-M filters on all I/O lines. Group all I/O lines together in a designated I/O area of the PCB.
• Shunt capacitors used in I/O filters must have a very low impedance connection to chassis.
• Use a power entry filter on the dc power line (both C-M & D-M)
• Most products in plastic enclosures need to be provided with an additional metal reference plane.
• Consider the use of board level component shields where applicable.
• Ground all heat sinks.
Note: Clock means any h-f periodic signal (e.g., CLK, RAS, CAS, ALE, etc.)
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