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Biasing Transistor in Weak Inversion

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taik

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Hi all,

I have just started to work on Low Power Circuits and I tried biasing a NMOS transistor to produce nA current.

However, I discovered that the drain current is very sensitive to Vgs to the order of 0.001V.

Is this normal?

Also, is the small signal circuit for FET same for both strong inversion and weak inversion?
 

taik said:
Hi all,
I discovered that the drain current is very sensitive to Vgs to the order of 0.001V.
Is this normal?
Also, is the small signal circuit for FET same for both strong inversion and weak inversion?
Click to expand...

I suppose you mean small signal model, don´t you ?
I know that several FET models do not incorporate any weak inversion region at all. Thus, you must carefully select a proper model description.
For example, the program MICROCAP contains some different FET descriptions and some of them model the weak inversion region. In this context it is important to note that the behaviour in weak inversion is different from that in strong inversion (log relation between voltage and current).
 

Hi
The observation made by you correct . This phenomena can be proved from the charge Vs surface potential curve of transistor . Here The operating region of weak inversion transistor is very narrow. As the surface potential is a strong function of gate potential. The mathematical relation of transistor in weak inversion is modelled in a ieee paper published in 1977.
Please see the paper to get a better idea about it

bye
 

Keep in mind that the relationship is exponential
 

Many times the models provided for subthreshold operation are not very accurate and hence we usually avoid putting trasistors in sub0threshold, except for current mirroring transistors.
 

taik:

It sounds like what you are saying is that the transconductance per current ratio is high for a MOS in weak inversion. If that is what you are saying, you are correct.

The transconductance (gm) of a MOS in weak inversion can be coarsely calculated as gm = Id/(n*Ut). n is typically between 1.3 and 2.0. Ut is the thermal voltage (KT/q) and is on the order of 0.025. This means that, for a 1mV change in gate voltage, you would see about a 2-4% change in current! In some places, this is good (such as the input pair of an amplifier), and some places it is not so good (matching in a current mirror).
 

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    doenisz

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hi JPR,

yes, that would mean my current mirror must be providing current to the accuracy of 0.01v. i mean in our strong inversion design, current slightly off is still acceptable but in weak inversion, this isn't the case. was wondering how to design such sensitive circuit...
 

taik,

There are a few things that can be done to improve the matching.

The first is to increase the size (area) of the transistors.

The second is to bias the transistor out of weak inversion. If you make the transistor a long channel length with a small channel width, it can push the operation to moderate or strong inversion.

A third option is to introduce a source degeneration resistor, which would act like the emitter degeneration resistor in a bipolar current source. The problem with weak inversion is that the current levels are small, so this resistor might be very large. For this reason, changing the size of the transistor is preferred.
 

Under inversion from Willy sansen's notes, you will have three inversion region: weak inversion, strong inversion and velocity saturation region and those depends on how hard you bias the Vgs.

IDS in strong inversion resembles (Vgs-Vt)^2 law, while weak inversion is an exponential relationship and velocity saturation varies linearly with Vgs, so your question should vary a lot in weak inversion, which is normal.

Small signal model does not depend on region, all you need is to add gm, rds, vgs, etc..
 

supreet_95 said:
Many times the models provided for subthreshold operation are not very accurate and hence we usually avoid putting trasistors in sub0threshold, except for current mirroring transistors.
Click to expand...

You don't normally use subthreshold in current mirrors
 

For analog signal processing in the log domain you always operate the current mirrors in the subthreshold region.
 

LvW said:
For analog signal processing in the log domain you always operate the current mirrors in the subthreshold region.
Click to expand...

That may be the case, but isn't normally matching worse in the case of current mirror transistors in sub-Vth regime?
 

LvW said:
For analog signal processing in the log domain you always operate the current mirrors in the subthreshold region.
Click to expand...

I thought that only the transitors within the translinear loop in log domain needs to be weakly biased. The others transitors (like current mirror) can be strongly biased.
 

wpchan05 said:
I thought that only the transitors within the translinear loop in log domain needs to be weakly biased. The others transitors (like current mirror) can be strongly biased.
Click to expand...

Yes, they can - thats true. I was thinking only on the current mirrors within the translinear loop.
 

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