Questions about VHDL-AMS language

Hi there,

I am new to VHDL-AMS. I would need to use VHDL-AMS to do system modeling. I have some queries about this language as below, please kindly provide any relevant informatons accordingly, thanks in advance.

1. I am trying to use VHDL-AMS to do Mixed-Signal behavioral modeling for IC block. My target is to produce some behavioral blocks which will help to speed up total simulation time during LSI design. Anyone please provides any comment about WHY VHDL-AMS would provide faster simulation speed compare to SPICE and other modeling techniques? and HOW to achieve it? What are the major concerns in this area?

2. I am planning to use ADVanceMS from Mentor Graphics to design my blocks. Please comment about the performance of ADVanceMS compare to other tools (e.g.: Cadence AMS designer, Dolphin SMASH, Synopsis Saber and etc)?

3. Currently in which industry VHDL-AMS is widely used?

4. Which companies in the world (except EDA vendor) are really putting resources to develop their design by using this language?

5. What are the career prospect for one`s who are well-versed with VHDL-AMS?

6. What are the main differences between VHDL-AMS and Verilog-AMS? Which one is more powerful and more popular?

Any comment is welcome. Thanks

vhdl ams operators

About your first question : Why VHDL-AMS is faster in comparision with SPICE because VHDL-AMS is a behavioral (top-down design) and SPICE is a netlist (Bottom-Up design). So the signal propagation in SPICE case will be more than in AMS case.

Second question : It's difficult to compare the performance of those equivalent AMS designing tools. Its depends on user familiar only. My friend always find comfortable with CADENCE but i only enjoy SYNOPSYS and Dolphin Smash.

Thirdly : In which industry AMS is used ? Obviously ASIC design. But remember that the simpler the programing language is, the harder it can be realized. We can come to it thru one popular example : A very simple operator * (multiply by a constant) may indicate the amplification process. But to realize it, our link and target ibrary must contains a generic amplifier( or at least few tenth amplifier each with different gain ). Hence by expanding our interest to AMS, we need a very strong and well-updated library designing team. It's the barrier to AMS.

Question no 4 : Which companies prefer AMS ? Plz refer to Google.com .... From my poor knowledge at this moment HSpice still their interest and it will remain for at least few tenth years more ....

Question no 5 : Career prospect for one who are well with AMS .... From my case i can say that it should be unemployed .... ( relax i'm just joking ) ... Its depends on you ...

Question no 6 : Conceptualy there is no different between VHDL-AMS and Verilog-AMS except those operators in Verilog are all most symbolized but VHDL are not.... They are equivalent. If you are new to AMS, it'd better to go for Verilog-AMS in stead of VHDL-AMS.... Verilog is more popular in industry.

VHDL-AMS

Hi atena,

regarding Q5, i think VHDL-AMS designer only has advantage to master VHDL knowledge then excel to ASIC industry. Else, just stay in university to make further research about it.....

However i heard VHDL-AMS is popular in Europe automotive industry. Anyone minds to provide some information about it...thanks

VHDL-AMS

To be master in AMS we must be good in both digital and analog design and analysis otherwise we are just the typists ...
Stay in university and make futher research, uhm it may be a not bad idea in US or Europe ....