Why do we use test bench to check a program?

Hello friends,

I programmed an application and checked with the modelsim and chipscope pro analyser to test the functionality of the application.

Is it necessary to write a test bench in order to check the program or is it okay to check it in the modelsim?what is the main use of writing the test bench when we have modelsim and chipscope pro analyser?

I came to know that in interviews they ask the questions like

How did you test your program?or how did you verify your program?

my answer to the above question will be "i verified my code with modelsim and chipscope...
is my answer correct or what should i answer to such questions as i verified my program only through the modelsim and chipscope.

TEST BENCH

I say the truth that i hate to work with ModelSim or any Graphical User Interface tools very much.

1st disadvantages is : GUI cant provide you a simulation vector which can simulate your circuit for a long duration. As u can see, with GUI you have to manually enter each every values of signals.

2nd disadvantages is : GUI cant help you to dump or back-annotating the switching activities of the circuit nodes. This VCD or SAIF file is the irreplacible input of Power Estimation tools.

Testbench can solve for you both 2 above problems.

Re: TEST BENCH

yes ,I like to write script to do the test bench ,you can try to do this and solve this problem!

Re: TEST BENCH

2nd disadvantages is : GUI cant help you to dump or back-annotating the switching activities of the circuit nodes. This VCD or SAIF file is the irreplacible input of Power Estimation tools.

i did not this point.Can you please be more clear.
Is it irrelevent answering the question of tetsing by saying that i have checked with modelsim or chipscop..

If my program is very huge like 10000 line is it better to test with chipscope?or should i write the testbench itself..

TEST BENCH

Tan said:

If my program is very huge like 10000 line is it better to test with chipscope?or should i write the testbench itself..

Click to expand...

Obviously testbench is the most efficient option in this case. But be careful with the problem of global signals and local signals.

Tan said:

i did not this point.Can you please be more clear.

Click to expand...

When you go to ASIC Design and Analysis you may face the problem say of estimating power consumption of your circuit. Your circuit is basicaly a death design, you give the virtual life to it by simulating it or in other word you force it to work. During the simulation the switching activities of the circuit nodes capacitances will cause the dynamic disspation ( including both Switching diss and Internal Diss ) which generaly occupy more than 95% of total power consumption. If you do not use testbench in the simulation process, you can not capture the Switching Activities of your circuit and hence can not do further power analysis.

Re: TEST BENCH

Rather than the number of lines, what is more important is the complexity of your design. More the complexity, more the test cases you need. Testing all the possilbe condtions using Modelsim can be very cumbersome. If you write a test bench or multiple test benches to test the various conditions, it would be more convenient and efficient. With a test bench you can have a better control over your test cases. Just saying that you tested with Modelsim or Chipscope will not be a very good answer i suppose, since even for a very simple design writing a test bench is the most common verification procedure.
Even at a later stage if you have to do gate level simulation with the netlist generated by the synthesis tool, with slight modifications the same test bench can be used and you can cross verify your pre and post synthesis simulation results.

Re: TEST BENCH

Thank you so much for your answers folks..
now i have to start writing a test bench for my complex code