Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

PLL Bandwith Question

Status
Not open for further replies.

mouzid

Full Member level 5
Full Member level 5
Joined
Jun 22, 2007
Messages
248
Helped
9
Reputation
18
Reaction score
0
Trophy points
1,296
Activity points
2,876
Hi,
I have two question on Bandwith and Phase margin.

What does mean that a System has a wide/narrow bandwith and Phase margin.

What relation exists between Bandwidth and Jitter.

I hope that I'm not saying somethink stupid. :D
 

Whao !
I have another question:
Is my last question is too stupid or too difficult ?
 

hi

As the phase margin is large enough it means the system is more immune to noise which can make oscillations ( need more explanation??)

the bandwidth of a system depends on the application, we always make the BW of application slightly higher than that of applications so as to minimize noise ( as jitter )

ask any question you want but press helped me button!!
 

    mouzid

    Points: 2
    Helpful Answer Positive Rating
medra said:
hi

As the phase margin is large enough it means the system is more immune to noise which can make oscillations ( need more explanation??)

the bandwidth of a system depends on the application, we always make the BW of application slightly higher than that of applications so as to minimize noise ( as jitter )

ask any question you want but press helped me button!!

Thanks. I pressed the button.

I need an in depth explanation. suppose that you have a tranceiver and a receriver. The tranceiver sends a set of bits to the revceiver and that each uses a PLL of Fpll Hertz.
Suppose that the receiver and the transceiver are synchronous (but not using the same PLL). Suppoe that the jitter is 1/100 of the period of one cycle what should be the Bandwidth of the PLLs ?
 

hi again
the jitter is noise;that means that there is no relation between jitter and bandwidth
I may limit jitter by limitting bandwidht,that's it
I will give you an easy example:
if you have a receiver that will recieve from 1MHz-3Mh then its BW 2MHZ ,if there is noise does the BW change?? os course no,will you increase the BW to help noise pass?? of course no
I hope you got it
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top