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Questions about designing LDO

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LDO questuionair???

for maximum current load

Added after 4 minutes:

if it is in saturation .. than for the maximum current than the pass element size is too large.. and Gm is also too high... than how to make out the EA specs
from this
 

Re: LDO questuionair???

From ur sim results... check the gate capacitance you get for ur pass device. Now the load spec for ur EA becomes this gate cap + miller effect.

so ur amp shud be able to drive this capacitive load.

Also try adding a buffer at output of amp so that parasitic pole dosenot degrade stabilty of loop...

hope this gives you some initial direction for EA design!! :)
 
Re: LDO questuionair???

ashish_chauhan said:
From ur sim results... check the gate capacitance you get for ur pass device. Now the load spec for ur EA becomes this gate cap + miller effect.

so ur amp shud be able to drive this capacitive load.

Also try adding a buffer at output of amp so that parasitic pole dosenot degrade stabilty of loop...

hope this gives you some initial direction for EA design!! :)
Click to expand...

Thanks ashish..

my gate cap is as high as 25pf for my load of 80mA

how do i place my poles of EA with respect to output pole given by the "pass element" and output load cap???

i dont think the poles of EA and poles given by passelement are independent of each other...
 

Re: LDO questuionair???

Yes, you are right.. output pole(p1) and the pole at EA output(p2) are dependent on each other... and many times very close as well ( when EA is not buffered).

For this you need to make Ro of EA low so that EA pole moves out.
and then add a zero in between p1 and p2.

by the what are the specs u are trying to chase.
 
LDO questuionair???

ashish_chauhan said:
Yes, you are right.. output pole(p1) and the pole at EA output(p2) are dependent on each other... and many times very close as well ( when EA is not buffered).

For this you need to make Ro of EA low so that EA pole moves out.
and then add a zero in between p1 and p2.

by the what are the specs u are trying to chase.
Click to expand...

my specs are 80mA (output max current) @ 130nm Process



if i decrease my Ro my current consumption will be very high for my EA...

How much current i can pump into EA for good efficiency..

in lot of datasheets i see they support EA with less current as low as 10.5uA

How is this possible with pass transistor cap being 25pF

Added after 17 minutes:

out put voltage is 2.8-2.9V with input voltage of 3.3V
 

Re: LDO questuionair???

Firstly .. 10u is not low! ...

how much current you should burn comes from ur bandwidth requierment which comes from ur transient specs...

secondly if u cant reduce Ro then try introducing a zero... in the loop
 
Re: LDO questuionair???

Are you making on-chip or off-chip cap LDO?

I think for on-chip cap LDO if you make the EA output pole is the dominant you can decrease its current consumption greatly.But you will consume more quiescent current in the pass element to make its pole far enough OR & you will add a zero in the loop.

It all depends on your transient specs as ashish_chauhan said.
 
LDO questuionair???

how can i add a zero in the loop???

Added after 1 hours 2 minutes:

is it ESR zero ...

Added after 2 hours 1 minutes:

what type of transistor for pass-element should i use from my process ..

LVT, HVT, native, nominal
 

Re: LDO questuionair???

Yes it can be esr zero ...

but you can add zero by adding a cap between ldo output and the feed back point.
This combination will also give u a pole... which you shud keep out of ugf.

Generally, with ur specs esr zero will suffice.
 
Re: LDO questuionair???

rajanarender_suram said:
what type of transistor for pass-element should i use from my process ..

LVT, HVT, native, nominal
Click to expand...

Low Vth devices will make the life hard for you; you should put the output DC level of the EA near to Vth (I mean difference between your input supply & the EA o/p node)in order to use a smaller pass element or & lower gain EA. You surely won't use native Vth transistor. You have the choices between:HVT&nominal.


see this:
 
Re: LDO questuionair???

quaternion said:
Are you making on-chip or off-chip cap LDO?.
Click to expand...

yes

quaternion said:
I think for on-chip cap LDO if you make the EA output pole is the dominant you can decrease its current consumption greatly.But you will consume more quiescent current in the pass element to make its pole far enough OR & you will add a zero in the loop.

It all depends on your transient specs as ashish_chauhan said.
Click to expand...

what is if off-chip cap is used and i make EA pole as dominant one???
 

Re: LDO questuionair???

rajanarender_suram said:
quaternion said:
Are you making on-chip or off-chip cap LDO?.
Click to expand...

yes
Click to expand...

what do you mean by yes ? [Off chip or On-chip]

rajanarender_suram said:
what is if off-chip cap is used and i make EA pole as dominant one???
Click to expand...

I think in this case you are killing yourself ;as for off-chip the LDO output pole will be at very low frequencies & you wants to make the dominant pole is at the EA output & so to get good phase margin(if you managed to get) you will get very bad transient response.
 
LDO questuionair???

off chip

Added after 2 minutes:

what is the better option in design??

1)pass element in linear region(for max current) & high gain EA
2) pass element in Saturation region and lower gain EA
 

Re: LDO questuionair???

Second option will be better ... the loop shall be easier to stablize.
 
Re: LDO questuionair???

ashish_chauhan said:
Second option will be better ... the loop shall be easier to stablize.
Click to expand...

Yes, by making a lower gain faster EA ;So its output pole will be at high frequency,and the Pass element will have considerable gain [in saturation or sub threshold] & the dominant pole at its drain.
 
LDO questuionair???

lower gain EA will give me feedback error(i.e if vref=1.2V my feed-back voltage will be 1.22V) is this is ok with the designs

Added after 6 minutes:

How much lower can EA gain can be???


my loop gain cut-off freq is at 10K and gain of 60dB at 80mA load..

&

it is 10Hz and 105db at 0A load..

what should i do to decrease this cut-off freq of the loop (without disturbing the off-chip cap value)
 

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