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are these layouts manufacturable?

Manufacturable?

  • Yes, thats totally ok

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  • No

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  • yes, but not recommended, since

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seen25

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ic layouts and overlapping

they passed drc, but I am wondering

I attached two files,
in the first one, poly curls over the active, is it allowed?

in the second, one the pmos is turned 90 degrees,
 

yes you can have 90 degree or even 45 degree gates but you will get size discrepencies.

As long as the poly does not overlap the active 50/50 (example) it would not fail drc, there will be miniumum spacing between poly to active overlap.
 

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    seen25

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That's correct. It will be perfectly doable.

As stated before, you can perfectly have 90 or 45 degrees bend gates (actually is an usual technique in big MOS, in order to gain effective transistor area...)

In this case you might consider that the "real" silicon transistor will be slightly different to the symbol values placed in the schematics...

Beyond that, if no rule is violated (that's the case) DRC will be clean and that's correct.
 

    S

    seen25

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The layout should be fine as long as DRC/LVS passed...and if you're circuit designer will agree with you.
 

DRC only check the violation for manufatured, they do not consider the parasitics, if you want performance and high yield , you should modified the layout
 

1) in digital we can use any orientation , but in analog we should follow same orientation.

2) DRC and LVS no problem , but overlapping will produce parasitic capacintance that increases delay, as possiblly we must avoid overlapping.

i think these are correct . can anybody comment pls.

Added after 1 hours 40 minutes:

we can follow different orientations in digital, but in anlog only we must follow same orientation for matched transistors, because the transconductances of the transistors are same which are placed in same orientation, this will avoid current mismatches.
 

gksivas said:
in anlog only we must follow same orientation for matched transistors, because the transconductances of the transistors are same which are placed in same orientation, this will avoid current mismatches.
Click to expand...

Is this also related to the effect of crystal orientation so we make matched transistor with same orientation?
 

quaternion, That's correct, MOS transistors oriented in the same direction match better than those with different orientation due to the anisotropic nature of monocrystalline silicon.
 

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