AdvaRes
Advanced Member level 4
Hi members,
I'm using the book of Gadner as a reference to understand how PLL is designed and how works its differents blocks. However when I tried to understand in depth these issues, I noticed that the book as well as the majority of the papers and Books does not discuss the particular cases and particular situation in the functionning of the pll.
I need your help to understand these undiscussed issues.
Let consider a PLL composed of a PFD, a CP, a Filter, a VCO and a frequency divider.
1- The PFD is used detect the frequency and the phase.
One crucial case not discussed is when the reset signals comes at the same time (or before a short time) with the clock signal that drives the PFD.
In that case, the DFF concerened by this clock signal does not set and the VCO voltage will change in the opposit direction. This phenomenon is repeated undefinetely and VCO Vtune will oscillate.
How can we resolve this problem ?
2- When the PLL locks the VCO Vtune stabilise at Vf. If I have well undestood, the filter is designed using as input informations Vf and the CP's current Icp.
The transfert function of the filter is the Impedance Z(s)=Vf(s)/Icp(s).
If we do the computation we can determine all the caracteristics of our filter in terms of Resistance and capacitances. But when we use our filter inside the pll we should not be surprised if the expected results are not found. In fact that is normal since we ignored the additional Impedance of the VCO input.
How can we determine the VCO input before the design of the filter so that the total impedance Z(s) includes the impeance of the VCO input ?
All your replies and comments are Welcommed.
Regards,
Advares.
I'm using the book of Gadner as a reference to understand how PLL is designed and how works its differents blocks. However when I tried to understand in depth these issues, I noticed that the book as well as the majority of the papers and Books does not discuss the particular cases and particular situation in the functionning of the pll.
I need your help to understand these undiscussed issues.
Let consider a PLL composed of a PFD, a CP, a Filter, a VCO and a frequency divider.
1- The PFD is used detect the frequency and the phase.
One crucial case not discussed is when the reset signals comes at the same time (or before a short time) with the clock signal that drives the PFD.
In that case, the DFF concerened by this clock signal does not set and the VCO voltage will change in the opposit direction. This phenomenon is repeated undefinetely and VCO Vtune will oscillate.
How can we resolve this problem ?
2- When the PLL locks the VCO Vtune stabilise at Vf. If I have well undestood, the filter is designed using as input informations Vf and the CP's current Icp.
The transfert function of the filter is the Impedance Z(s)=Vf(s)/Icp(s).
If we do the computation we can determine all the caracteristics of our filter in terms of Resistance and capacitances. But when we use our filter inside the pll we should not be surprised if the expected results are not found. In fact that is normal since we ignored the additional Impedance of the VCO input.
How can we determine the VCO input before the design of the filter so that the total impedance Z(s) includes the impeance of the VCO input ?
All your replies and comments are Welcommed.
Regards,
Advares.