How to translate system level PLL spec to ckt implementation

pll implementation

I am studying PLL through reading a few PLL related books and tutorials, they all start with the similar system level block diagram and analysis shown in the attached file. However, when it comes to the ckt level implementation, I am a little bit lost on how the system level specs are translated into the ckt level implementaion. For example the PFD (Phase Frequency Detector) block in the system level is normally modeled with the the parameter Kp, but the ckt implemention is nothing more than two D Flip-Flops for edge detectors and the outputs are two digital signals Up, Down, so my quesion is how the parameter Kp
in the system level is associated with Up/Down? Similarly, the VCO block in the system level is represented with the system parameter Ko, but the
implementation is nothing more than a rign oscillator (assuming delay cell implentation) with a tune voltage, how can I translate the spec Ko into the circuit implementaion?




Thanks,

system-level analog design pll

Hello,
Concerning the PFD/CP, the gain Kp is controlled by the charge pump and the loop filter capacitor. Kp is proportional to Ip/Cp, where Ip is the charge pump current and Cp is the loop filter's capacitor.

Concerning the VCO's gain Ko, the gain is controlled by how much you vary the frequency for certain voltage. For the ring oacillators for example, how much the delay can be varied wrt the control voltage controls the VCO gain. This can be performed by varying delay cells current, or by varying load's resistance (for differential ring oscillators).

ckt design of pll

Dear ieropsaltic:

Thank you for the reply, it's now getting clearer now. A couple more questions though.
1. If Kp is only to do with the charge pump, what is the design spec for PFD itself?
2. How to determin the number of stages in the ring oscillator?
3. An article I read cited that the loop filter is THE most crucial in the PLL design, "The filter is very important in the design of the PLL since both the natural frequency and the damping factor are a factor of the filter response. In fact, we can say that the design of PLL is almost entirely dependent on the design of the loop filter", , however, for the most popular 2nd order loop filter, it's just one R and two C's, so where is the challenge in ckt implementation? Is the challenge more in the system level to decide the order of the filter?
4. Also, the system level block diagram alwasy uses the multiplier as the Phase Frequency Detector and with a little trigonometric manipulation, a nice two terms of equations can be derived that shows the phase difference and the twice the signal freq. term. But how does this high level multiplier being translated into just two edge DFF in ckt implementation and can still hold the theory valid?

Thanks,

pll spec

hdmi said:

I am studying PLL through reading a few PLL related books and tutorials, they all start with the similar system level block diagram and analysis shown in the attached file. However, when it comes to the ckt level implementation, I am a little bit lost on how the system level specs are translated into the ckt level implementaion. For example the PFD (Phase Frequency Detector) block in the system level is normally modeled with the the parameter Kp, but the ckt implemention is nothing more than two D Flip-Flops for edge detectors and the outputs are two digital signals Up, Down, so my quesion is how the parameter Kp
in the system level is associated with Up/Down? Similarly, the VCO block in the system level is represented with the system parameter Ko, but the
implementation is nothing more than a rign oscillator (assuming delay cell implentation) with a tune voltage, how can I translate the spec Ko into the circuit implementaion?




Thanks,

Click to expand...

First using matlab choose the parameter you concert, then use circuit to realize it.

p l l ckt

Try to vary the controlled voltage and measure the output frequency of VCO to see if the gain of VCO is met. If not, adjust the sizes of delay cells of the VCO.

Re: How to translate system level PLL spec to ckt implementa

Hello,

1- For PFD, I think you need high slew rate at the input. Also, you need to control the reset the pulse width to mitigate the dead zone effect of the charge pump.
2- For the ring oscillator number of stages, that depends on the different phases you need and the frequency required. Less number of stages (but greater than 2) can ease implementation at higher frequencies. But if you need IQ signals for example, you'll need 4 stages.
3- The loop filter is very important because it controls required loop BW, phase margin and thus stability and the settling time. However, other parameters are also important as they contribute at phase noise transfer functions. The challenge at the filter design is choosing the required BW as there's a trade off between contributions of different block wrt BW (VCO & delta sigma see HPF effect while other blocks see LPF effect). Also, you need low BW to filter spurs while you need large BW to ensure fast settling, while maintaining stability. So, it's more involved in system design rather than simply 2C and R. Also, filter's order is challenging to filter spurs, have roll off at the expense of more difficult stability.
4- The multiplier is actually an analog phase detector that was very popular many years ago. However, it's just one way to implement phase detector. Other ways include XOR phase detectors, PFDs .....etc. So, both multipliers and PFDs are 2 different ways to implement the phase detection action. Some people may use multipliers at system level to model the PD at system level, however the more common way is to model it as a subtractor, specially at s-domain, to illustrate the effect of negative feedback.

Regards.

Re: How to translate system level PLL spec to ckt implementa

But don´t overlook the fact that the linear PLL model with a subtractor works only under three conditions:
1) In-lock (that means both frequencies are already equal)
2.) The input signal is a phase deviation
3.) The phase deviation must not be greater than 30 deg.

Otherwise, the linearizing actions are not allowed.
LvW