firefoxPL
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Hello, I am currently porting demo from Xilinx for XUPV2P board for controling VDEC from Verilog to VHDL and I have problem with understanding one phrase:
TRS is a 1-bit signal, I did something like this in VHDL but I am not sure whether it is right:
In fact it is very probable that this is wrong and thats why the project doesn't work
Code:
assign TRS = ((~|YCrCb_rg2[9:2]) & (~|YCrCb_rg3[9:2]) & (&YCrCb_rg4[9:2]));
Code:
TRS <= ((((YCrCb_rg2(9) nor YCrCb_rg2(8)) nor (YCrCb_rg2(7) nor YCrCb_rg2(6))) nor ((YCrCb_rg2(5) nor YCrCb_rg2(4)) nor (YCrCb_rg2(3) nor YCrCb_rg2(2))))
and (((YCrCb_rg3(9) nor YCrCb_rg3(8)) nor (YCrCb_rg3(7) nor YCrCb_rg3(6))) nor ((YCrCb_rg3(5) nor YCrCb_rg3(4)) nor (YCrCb_rg3(3) nor YCrCb_rg3(2)))))
and (((YCrCb_rg2(9) and YCrCb_rg2(8)) and (YCrCb_rg2(7) and YCrCb_rg2(6))) and ((YCrCb_rg2(5) and YCrCb_rg2(4)) and (YCrCb_rg2(3) and YCrCb_rg2(2))));