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what are the limiting factors for high resolution CT SD ADC?

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safwatonline

safwatonline

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CT SD ADC

i was wondering what are the limiting factors for high resolution CT SD ADC?
i.e. why i cannot find some 20bit or more CT SD ADC
 

CT SD ADC

I am not an expert on this but answer to your question is: Oversampling converters samples the input signal many times so oversampling and averaging results high resolution at the end. CT SD are used in RF frequencies and oversampling clock needs to be too high in order to oversample enough to get higher resolution. Process dependent clocking speed limits the resolution. Also for RF applications often 6 to 10 bits of resolution is enough.

I hope this helps.
 

CT SD ADC

actually, i don't agree. why are u limiting the use of CT ADC to RF freq.
 

CT SD ADC

I think a basic limiting factor there is unideality of components: key, opamp ;noise in MOS, CAP, RES; unideality C(V) character capacitance; you can get more than 20 bit of monotony but not linear.
 

Re: CT SD ADC

There are continuous-time implementations which achieve 118 dB of DR and are used in FM Rx
 

    safwatonline

    safwatonline

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Re: CT SD ADC

I think SD adc is not appropriate in low frequency application such as instrument measurement which require very high resolution(18bit more), since the resistor's thermal noise is quite large at low clock frequency. The CT sd ADC's dominant application is in high bandwidth communication and the oversampling ratio is low.Also, the audio can use CT sd ADC.
 

Re: CT SD ADC

I disagree Casol

In SC, you would need a very large Cap to decrease thermal noise ( kT/C ). Likewise, in a continuous-time implementation, you can use a large Cap with smaller resistance to get the same goal.

I might be wrong, but that's what I guess
 

Re: CT SD ADC

I think it apply on the DAC's clock jitter.
 

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