Basics in Layout, some fundamental questions

lambda rules

Hi
I am new to layout design. I am having some basic questions.

1) In schematic level we are using transistors with 4 lead, namely source, drain, gate and bulk, but while we are doing Layout we will consider only three leads namely source, drain and gate. Why we are not considering bulk?

2) How to convert lambda rule to micron rule?

3) Can you sugest me some links to get AMI 0.6u design rules?

Basics in Layout

1/ The bulk is not considered since it is connect to VDD or VSS with Via.

Re: Basics in Layout

sivarajm said:

1) In schematic level we are using transistors with 4 lead, namely source, drain, gate and bulk, but while we are doing Layout we will consider only three leads namely source, drain and gate. Why we are not considering bulk?

Click to expand...

We have to consider to which bulk it is connected.
Eg : Analog ground and digital ground may be different.

Let me know if you are still not clear.

Regards,
Sandeep

Re: Basics in Layout

Normally in Digital design, people will take care of subatrate & well connection at the SOC level.. I dont know How it is implemented in Analog circuits..Can anyone please explain How it is implemented in Analog circuits?.

Basics in Layout

hi Sandeep

can u tell some more details of ur point.

In schematic level we use to connect the bulk to vdd fr PMOS and to vss for NMOS.

When we designing the Layout we are not considering the bulk connections.

"AdvaRes" said that bulk will not be considered. Is der any spl. reason.

Re: Basics in Layout

chap,

You will definetly consider the bulk terminal also for each and every transistor.
You can try with some example by not having tap (Bulk connection) and run LVS.

You will get error that your transitor bulk is not connected. (i.e open)

But one thing you need to remember is always your bulk connection for some bunch transitors will be same and you will put all of them together. So if you have any more doubts you can definetly come across. Thank You.

Varma.

Basics in Layout

IN the layout you do not have the bulk contact because before contacting the bulk you´re expected to join all the transistors that can be placed on the same bulk and then you must place a BULK CONTACT(s), by choosing a good place for it (in such a way you have it (or them) as centered as possible or as distributed as possible and connected to the correct potential.

Hope this helps.

Basics in Layout

1) In layout, indeed we are considering the connection to the "bulk" terminal, depending on the MOS type and/or process the bulk must be connected by appropriate placement of WELL-TAPs, somewhere within its well boundary. For CMOS processes, Layout Engineer cares for the Latch-up while considering the placement of the TAP.

RF-MOS devices, or Isolated-Well-MOS devices you will find the "bulk" connection inside the isolated well itself, For certain HF-MOS devices there could be 7 terminals as well.

A point to be noted, for an ordinary MOS, if you try to answer the question "where is the bulk terminal of a single MOS device located?" you will get the reason, why 4-terminal ordinary MOS device need not have the 4th terminal(B) connection from a metal1 layer localized on it.


2) Lambda rule to micron: I believe, the historic thumb rule is lambda = 1/2(half) min_gate_length.
1 lambda is 0.3um, if it is 0.6um technology.

However, back in history, DRC rules were usually of two types "scalable" (lambda-based) and "micron-rules".

Later, as layers did not scale in similar fashion, in sub-micron & sub-wavelength era, Lambda rules did not survive through the sub-wavelength evolution.

Lambda-rules did pretty well during 3um - 1um days - in the middle, during transition from 1um --> sub-wavelength, foundries used to do with the Lambda tweaking for selective layers/rules. So, the specifics of the translation of lambda-rules you must follow foundry DRM, don't just use 1 lambda is 0.3um!

Number of Contacts

Thank you for you valuable reply. Its very much useful for me.

Added after 3 hours 23 minutes:

hi..

I am not getting why more number of contacts are needed?

kindly refer the following figure. Its an inverter layout.

In that 1 + 1 (2) contacts are alone for PMOS right?

what is the need for going 3 + 3 (6) contacts? Is der any special reason for more number of contacts?

Re: Basics in Layout

it's for higher reliability of the connection.

Re: Basics in Layout

hi..

You have said for more reliability more number of contact are used.

Can you tell me wer can I get more detail about the point which you have said.

Basics in Layout

It has to do with TUB or BULK resistance, as soon as you increase and distribute more contacts all along the tub area, you'll have a better distributed tub potencial and less resistance asociated with the tub difusion.

Re: Basics in Layout

sivarajm said:

hi..

You have said for more reliability more number of contact are used.

Can you tell me wer can I get more detail about the point which you have said.

Click to expand...

i believe hastings discussed it in his book.

Re: Number of Contacts

sivarajm said:

Thank you for you valuable reply. Its very much useful for me.

Added after 3 hours 23 minutes:

hi..

I am not getting why more number of contacts are needed?

kindly refer the following figure. Its an inverter layout.

In that 1 + 1 (2) contacts are alone for PMOS right?

what is the need for going 3 + 3 (6) contacts? Is der any special reason for more number of contacts?

Click to expand...

More number of contacts are required at the source side than the drain side....

Basics in Layout

Just in case it is not 100% clear: multiple contacts are used for two reasons: 1) in analog design the contacts are in parallel, so they effecively lower the series resistance of the via contact 2) in case during manufacturing one via isn't fully contacted, there are "backup" vias. Depending on the sensitivity of the connection to resistance you may decide upon the number of vias; e.g. since a transistor depends on the GS function, it makes sense to use more vias at the source side.

Re: Basics in Layout

nschutten said:

Just in case it is not 100% clear: multiple contacts are used for two reasons: 1) in analog design the contacts are in parallel, so they effecively lower the series resistance of the via contact 2) in case during manufacturing one via isn't fully contacted, there are "backup" vias. Depending on the sensitivity of the connection to resistance you may decide upon the number of vias; e.g. since a transistor depends on the GS function, it makes sense to use more vias at the source side.

Click to expand...

To add more.. We need to see that there is less cap on the drain side to reduce the cap. Else this cap will be considerable. But if the cap at the source side is more it is better as it is connected to the Power signals.

Added after 3 minutes:

sivarajm said:

hi Sandeep

can u tell some more details of ur point.

In schematic level we use to connect the bulk to vdd fr PMOS and to vss for NMOS.

When we designing the Layout we are not considering the bulk connections.

"AdvaRes" said that bulk will not be considered. Is der any spl. reason.

Click to expand...

Sivarajm,
The info provided by "AdvaRes" was wrong. We do consider the bulk connections in Layout.
We try to see if we can put the same transistors having same bulk connections together so as to reduce the area sometimes....

Regards,
Sandeep

Re: Basics in Layout

Have you gone through Latch Up ur queries will be over.....

Basics in Layout

we do consider bulk connections ..... connecting well and substrate contacts to approprite potentials via contacts.... You must have seen guard rings ... the are ring of contacts.. it also reduces the resistance rather that single contact..