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Two methods of doing VCO layout

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AdvaRes

AdvaRes

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Hi members,

In practice, VCO layout are done Like fig 1 or like fig2.

What are the constraints ?
 

Re: VCO lay out question

Layout to reduce parasitics cap on the load so I would choose second one
 

    AdvaRes

    AdvaRes

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Re: VCO lay out question

AdvaRes said:
Hi members,

In practice, VCO layout are done Like fig 1 or like fig2.

What are the constraints ?
Click to expand...

I think fig2 is better, because the three parts are the same conndition, especially parasitic cap and resistor.
 

    AdvaRes

    AdvaRes

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VCO lay out question

Thanks my friends,
Is there another advantage of the second configuration to convince me to adopt it ?
That Is really a challenge for me. In fact the figure 1 has the advantage to have a small area (around 75%) compared to the 2nd.
 

Re: VCO lay out question

hi mady79,

can u please explain how "parasitics" will reduce in fig2.
 

Re: VCO lay out question

hi gksivas,

referring to the interconnect parasitics . you cannot reduce the gate capacitance of the next state and diffusion capacitance which are seen as the load.

hope this anwers your query .

Mady
 

    AdvaRes

    AdvaRes

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VCO lay out question

Hi

the drawback of the second solution is that, being the 3 blocks differently oriented, mismatch between them is higher.

I hope it can help.

Mazz
 

    AdvaRes

    AdvaRes

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Re: VCO lay out question

hi mady,

i cant imagine that circuit.
in fig.1 three blocks are oriented in same direction.
in fig.2 they are oriented in different directions.

this is the difference i got between 2 figures.

can u tell me what is the difference between these two blocks.

thanku
 

    AdvaRes

    AdvaRes

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VCO lay out question

I will go to no.1.
The size of the delay cell each shouldn't be very big. So don't need to worry about the long wire from cell1 to cell3 at all. Also the layout can look more neat.
 

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