Hierarchical netlist vs flatten netlist

Wts the difference between hierarchical netlist and flatten netlist?

How to identify by seeing the netlist whether it is hierarchical or flatten?

Once the synthesis is over we will get the netlist and this netlist will be given to the backend design..So my question is will this netlist be flatten netlist or hierarchical netlist?? Or do the tool converts it into flatten netlist??


Reply me

Usually the first thing that these tools use to do is to flatten the hierarchy. I do not know in particular with synthesis, but DRC, EXT, etc. works like that...

hi,

flatten, is when the entire design is in 1 module (ie verilog, module, endmodule).
hierarchical is when you have more then 1 module for the entire design.


banckend tools are able to read in both flatten/hierarchical netlist.

hope this helps.

Thanks Tony

@Tony,

But usually in complex ASIC design we can't have all design entry in one module, generally we have many modules then that means we can't convert that hierarchical netlist to flatten netlist during synthesis.

Thanks

hi pintuinvlsi,

the netlist that vlsitechnology is referring to is a gate level netlist (after synthesis)
not rtl netlist (behavior code). Agree, rtl netlist is most likely hierarchical, but for gate level netlist (after synthesis)... it can be either hierarchical netlist or flatten netlist.

why can you not flatten the netlist after synthesis? place & route tools are smart enough to accept both hierarchical gate-level netlist and flatten gate-level netlist.
it really doesn't matter to the eda tools.


the only reason why hierarchical netlist would be chosen is for human read-ability and debug purposes. in fact, magma tools, you can read in hierarchical netlist and still flatten the netlist (physically), and still keep the hierarchical netlist( (logical). in other words, you still have both forms of netlist, hierarchical and flatten in one data base. i hope that wasn't confusing.

in the place & route tools, if you don't flatten the netlist, you wont take advantage of the cross boundaries optimizations.

hope this helps.

-Tony

hi ,

we flatten designs using data flatten command during design Preparation in magma. how do we preserve heirarchy of the netlist in magma?

thankz

Hi

pintuinvlsi has written "generally we have many modules then that means we can't convert that hierarchical netlist to flatten netlist during synthesis."

Is it correct?

In design compiler there is command available to flatten a netlist. So I think any hierarchical netlist of any size can be flattened using that command.