Shielding concept in detail( SI)

Can anyone explain me the shielding concept in detail ??

Why do we need to shield with Vdd and why do we need to shield with Vss??

Reply me

hi,

i cannot go into detail, but in general, we can shield a net in between a pair of vdd net or vss nets because these are constant signals and will not introduce any crosstalk. picking vss or vdd to shield with really depends on how accessible vss/vdd is to that net. when shielding a net, you can only pick vdd or vss, not both.



hoped this helps.

good luck.

Important point should be observed is since Vdd or Vss is constant level the parasitic coupling capaciatnce generated due to them is less as well as constant. Hence crosstalk noise or glitch produced by the aggressor is small and absorbed by the shielded net.

As the name indicates, the idea is to protect (or isolate) the items (lines, components, etc) you'll have at both ends of the shield.

If you have a switching (noisy) line or component and at higher or lower level you need to place a line or component that might be affected, there is where I recommend you to put the shield... In my particular opinion I prefer to limit the shielding just to VSS (GND in our chips) since I prefer to have a VDD line as clean as possible (even when the shield shouldn't be that much affected by the noisy element) because (more in the Analog world) you might have blocks needing a very clean supply (many times we dedicate one line just to that block...) so keeping a clean VDD is key...

IN the VSS (or GND) something you can do is to have two independent lines across your die, one "clean" just for block supply and other "noisy" that can be connecting your shieldings and your substrate contacts...

Hi Layoutmaster, What is Shielding net?. Is in the net which is going to the substrate connection?. I have never seen any shieldings.. Could you plz upload a screenshot or pic of the shielding?. I just want to see how it look like..

shileding will be done for minimize the coupling effect,generally high freq,and analog signals are aggresser nets,these nets cause SI problems,to minimize the coupling effect we do shelding net i.e is connected to GND this will decrease the coupling cap but it increase GND cap but overall SI timing will not effect.

Hi,
Pl check the following picture showing the CTS with only the Clock routed.
Clock net is shielded with VSS on both sides.

Hi

Clock shielding creates a guard ring around the clock net in the same layer as the clock net
and is tied to the ground rail. The purpose is to prevent a coupling capacitor from forming
between the clock net and another signal net. Instead a coupling capacitor is created between
the clock net and the grounded shield and the signal net and the shield. Any coupling cap to
the shield is merely a capacitor to ground. Therefore, no crosstalk should occur between the
signal nets and the clock net