Help me with VHDL code which produces the quadrature carriers for the signal mapper

hi guys,

I'm implementing a digital transmitter on fpga. can anyone help me with the vhdl code which produces the quadrature carriers for the signal mapper? how can I implement it without using any external oscillator?

Regards,

IF in fpga

Hi,
First you need to generate the desired IF frequency using the master clock input to the FPGA with an NCO( f_c +/- f_d i.e. carrier +/- doppler). Sample a full sine wave cycle with desired sampling resolution(say 3 bits) and build a lookup table (with suitable form say sign and magnitude). Using the NCO output, you can generate the in-phase signal directly from the look-up table and with a 90 deg offset, you can generate the quadrature-phase IF.

Regards,
VR

Re: IF in fpga

You need reference clock anyway, it should be fast enough to provide you IF, and your design should be able to operate under it. So don't bother yourself about FPGA realization of IF modulation, just create baseband signals, extract them using symbol-period clock, and then perform IF modulation externally.

Re: IF in fpga

will it not be more accurate to use a LUT for creating the carrier inside the fpga itself than taking the clock signal and changing the frequency the IF carrier?

Re: IF in fpga

Both solutions are possible. It depends basically on frequency range and additional requirements, which solution is more suitable.

Re: IF in fpga

No, you don't need to change any frequency - just use 2*symbol-rate clock for generation of appropriate BB signal within FGPA, and then external LO operating at IF for 2-dimensional modulation (meaning - use external modulator). That's all.

Now, to create, let's say - 140MHz IF carrier in form of LUT, you need (at least) 280MHz reference to clock your logic (as you know, you need at least 2 samples per one IF clock period for successful digital generation). There's nice bit of probability your design won't operate at such big clock frequency, even worse - if you're using 280MHz clock anyway, why don't you just double it's period with DFF to get 140MHz digital clock, results would be the same (i. e. just like in the case of using LUTs)? You'll need external analog filtering for this solution, fast DACs, etc.
For bigger accurance, of course, you'll need LUT with more than 2 samples (maybe - 4), controlled by faster clock (operating frequency is linear function of number of samples per period - for 4 samples per period you need 560MHz clock )...

Re: IF in fpga

See the following post



I think that the file I uploaded could help you in defining your design parameters.

Regards
Mowgli