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why 9 values in std_logic

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pwq1999

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i am wondering why ieee defines Std_logic with 9 values, and how it is implemented in FPGA.
'U'---Unintialized
'X'---Forcing(i.e. strong) unknown
'0'---Forcing 0
'1'---Forcing 1
'Z'---High impedance
'W'---Weak unknown
'L'---Weak 0
'H'---Weak 1
'-'--- Don't care

in digital logic design, we often use logic '1' and logic '0' and 'Z'. i want to know the difference between '0' and 'L', '1' and 'H' ,and so on.

How all those values are implemented in FPGA? are there some special resources available inside the Fpga ?

any input is appriciated!
Thanks in advance!
 

out of 9 values only 0,1,X,Z are synthesizable..........so we can implement only these 4 values on FPGA............
 

since only four values are synthesizable, i still cannot get it why they use 9 values, what other values are used for ?

thanks for your reply,amitgangwar_vlsi
 

in VHDL there are some constructs are only for simulation not for synthesis like...delays(inertial, transport, reject), textio, assert etc...
 

if they are only used for simulation, how can i used them?
thanks for your reply,amitgangwar_vlsi !
 

some constructs are used only till simulation level... these are used like..........textio is used for taking input at the time of simulation from a text file to your vhdl program and write back your output to the text file..... "after" statement is used for delay but it is not synthesizable... at the time of actual implementation you have to design a counter to count that time... OK
 

i know that textio is used to simulation,and the key word 'after' to describe the delay of hardware, but i just don't know how to used the 9 values in std_logic .
thanks all the same!
 

just find out the resolution table for 9 type of values.... according to which output value return on a signal when there are more than one driver drive that signal. that is called multiple driver problem. this is removed by the resolution table.
write a program and force different values to one signal and see the out put. in 9 values there is a sequence of strength, X has highest strength while Z has lowest... just read about resoultion table........

amit gangwar
 

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    pwq1999

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Most of them is for simulation for example if u drive a signal with to other signal at the same time for this the simulator doesnt know the correct value so cos of the std_logic it chooses 'X' for signal of if for a period of time your signal dosen't get value simulator assigns 'u' for it.

Added after 1 minutes:

and all of this is because VHDL had been desined for simulation purpose many times later that technology progressed it changed to support synthesising.
 

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    pwq1999

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Really thanks, amitgangwar_vlsi and hamed_sotoudi !
you two helped me a lot!
now i get the meaning and thanks again!
 

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