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This do not depend of the wire lenght, the wire lenght must be considered due to the added series resistance...
This is process dependent since it has to do with the metal thickness.
As mentioned in a post before, you must look for that information in your Process Specification, as Current Density data. It could be find in a DRD rules file, or any manual for your process.
The unit for critical current density is definitely mA/µm (current per width). Current density is independent from length, since it is defined as current through area (which in the case of CMOS technology is only width, since the height of each layer is constant and technologically determined).
In AMS 0.35 technology the value is 1 mA/µm DC. The specified value is at 110°C. This is can be understood as RMS value as well. In addition, the peak AC-current densities must not exceed 30 times the specified DC-value.
Also, and again it's process dependent (I'm not familiar with the one you're mentioning) you must consider if you'll have an "step coverage" (this depends on your line path).
In this case, the usual thing is to double the resulting width under normal calculations (in other words, you must consider the step as a place with a half of processe's mA/um normal density, actually what happen is that you have there a metal thickness reduction and electromigration can kill you in the long time)
The basic requirements is inclued in DRD,
if it is the digital, the width of metal 1 should be
the same with the metal in standard cell,
in analog, IR drop should be taken into consideration.
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