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Simulating post place and route modle

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snake0204

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Hi all,

When I synthesize my VHDL model XST synthesis reports says that the design can run at some 215Mhz, and when simulate the behavioral model (at 100 Mhz) every thing is fine. But when I try to simulate the post place and route model with the same test bench at 100 Mhz it not working at all. But it works fine if I decrease clk frequency to 25 Mhz. I am using ModelSim PE to simulate my models, and also don't have any timing or placement constraints on my design.

I don't really understand why the post place and route model is failing. Any ideas please!!

Tanks
Snake
 

After synthesis the timing report may be given 215Mhz but u check the timing report after PAR for the maximum frequency. after synthesis we get approximation but after place & route we get more accurate approximation of frequency of operation. In FPGAs many times the routing delay is much more than cell delay in ur design also may be route delay is more. because of that u better to use period constraint for ur required frequency.
 

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    snake0204

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Thanks for the help....i placed a global period constraint for the model but when I simulate the PAR model, non of the input signals are entering the input registers. I placed the pad to setup and clk to pad constraint as well but it is not helping. I attached the wave from modelsim. The third and fourth rows are start and state signals, the start signal is high on a +ve edge and pulled low on the next clk +ve edge,

IF CLK' EVENT AND CLK = '1' THEN
IF START = '1' THEN
STATE <= NEXT_STATE;
ELSE
STATE <= CURRENT_STATE;
END IF;
END IF;

Thanks for any help!!!
 

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