Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to perform a dither archi for 1-bit sigma-delta adc?

Status
Not open for further replies.
C

castrader

Member level 1
Member level 1
Joined
Jun 8, 2005
Messages
36
Helped
7
Reputation
14
Reaction score
1
Trophy points
1,288
Activity points
1,468
How to generate random code?

How to define dither voltage level?

I know that dither level is about LSB/2, I want to know how to get this level.

Can anyone give me some advice or architecture or papers?

Also can anyone tell me when design it, what need I take care mostly?

Thank you very much!
 

Schreyer discusses the topic in detail in his books on SD data converters.
 

What is the book name of "Schreyer" ?
 

generally, you can design a random (or pseudo random) sequence generator. you can vary the length of shift register to achieve better results. then add it to your modulator to make your signal busy enough.
 

    C

    castrader

    Points: 2
    Helpful Answer Positive Rating
take care not let quantizer overloading
 

    C

    castrader

    Points: 2
    Helpful Answer Positive Rating
I am afraid if dither is too large to keep quantizer overloading, how to select dither amplitude?
 

A SD modulator with 1-bit output and n-bit input could be controlled by an additional 1bit-dither input. Because the mean value of the dither sequence is 0.5 a systematic difference exist. For audio application it is not important.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top