eynasantiago
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Hi,
Please help in my project.
Design CMOS op-amp given the specs below:
Gain ≥ 70dB
Settling time ≥ 1µs
Input CMR (common Mode Range) ≥ ± 3V
CMRR(Common Mode Rejection ratio) ≥ 60dB
Output Resistance = Not applicable, 20pF capacitive load only
noise ≤ 100nV/Hz at 1KHz
Gain bandwidth project ≥ 2MHz
Slew rate ≥ 2V/µs
PSRR(Power Supply rejection Ratio ≥ 60dB
Output Swing ≥ 4V
Any reference or advise is highly appreciated..
thank you very much.
Please help in my project.
Design CMOS op-amp given the specs below:
Gain ≥ 70dB
Settling time ≥ 1µs
Input CMR (common Mode Range) ≥ ± 3V
CMRR(Common Mode Rejection ratio) ≥ 60dB
Output Resistance = Not applicable, 20pF capacitive load only
noise ≤ 100nV/Hz at 1KHz
Gain bandwidth project ≥ 2MHz
Slew rate ≥ 2V/µs
PSRR(Power Supply rejection Ratio ≥ 60dB
Output Swing ≥ 4V
Any reference or advise is highly appreciated..
thank you very much.