xtcx
Advanced Member level 1
- Joined
- Dec 22, 2007
- Messages
- 493
- Helped
- 65
- Reputation
- 130
- Reaction score
- 58
- Trophy points
- 1,308
- Location
- Bangalore, India
- Activity points
- 5,003
physdesignrules 372
HI everyone, I got this warning message in Generating program file under Xilinx ISE 8.2i.(VHDL)
Sample of my program,
Entity temp is
port (clk : in Std_logic;
clk_recov_op : out std_logic);
ARCHITECTURE Behaviarol of TEMP is
SIGNAL clk_recov,clk_recov_inv : STD_LOGIC;
BEGIN
clk_recov_inv <= NOT(clk_recov);
clk_recov_op <= clk_recov_inv;
PROCESS(clk) IS
{
\\
\\
\\
}
END PROCESS;
END Behavioral;
What does than error report mean?....In xilinx answers database, I saw it's something related to DCM. Like when there is no clk is input, the device can be put into stop mode and when the clk is in again, it shouldbe restored within some 200ms for dcm to operate safely.This should be manually done in Virtex4 devices of old type.In recent devices,they have a macro inside to take care of this..In my design,I have no dcm for clk multiply or divide...Only counters...and my clk is continuous....Though it's a warning,the message said it'snot a good practise,so I'm afraid about any timming issues...which brought me posting here immediatly...If anybody has got something about it,plz let it here....Thanks
HI everyone, I got this warning message in Generating program file under Xilinx ISE 8.2i.(VHDL)
WARNING hysDesignRules:372 - Gated clock. Clock net clk_RECOV_op_OBUF is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
Sample of my program,
Entity temp is
port (clk : in Std_logic;
clk_recov_op : out std_logic);
ARCHITECTURE Behaviarol of TEMP is
SIGNAL clk_recov,clk_recov_inv : STD_LOGIC;
BEGIN
clk_recov_inv <= NOT(clk_recov);
clk_recov_op <= clk_recov_inv;
PROCESS(clk) IS
{
\\
\\
\\
}
END PROCESS;
END Behavioral;
What does than error report mean?....In xilinx answers database, I saw it's something related to DCM. Like when there is no clk is input, the device can be put into stop mode and when the clk is in again, it shouldbe restored within some 200ms for dcm to operate safely.This should be manually done in Virtex4 devices of old type.In recent devices,they have a macro inside to take care of this..In my design,I have no dcm for clk multiply or divide...Only counters...and my clk is continuous....Though it's a warning,the message said it'snot a good practise,so I'm afraid about any timming issues...which brought me posting here immediatly...If anybody has got something about it,plz let it here....Thanks