inout port+testbench problem, verilog

verilog inout testbench

I wrote a testbench for my i2c code but it doesn't seem to work.

In the module SDA is an inout port.

In the testbench:

...
wire SDA;

reg SDA_reg;
OE = 1;
...
assign SDA = (OE == 1) ? SDA_reg : 1'bz;
...

I always write SDA_reg. The problem is that SDA always stays in Z and it isn't loaded. Does anyone has idea what I do wrong?
Thx,
krivan

inout verilog testbench

Have you plotted out SDA_reg in the simulator and are sure that it is not undefined?

What happens if you change the statement to:
assign SDA = (OE == 1) ? SDA_reg : 1'b1;
Does SDA go high?

If you change the statement to:
assign SDA = (OE == 1) ? SDA_reg : 1'b0;
Does SDA go low?

What I am trying to get at with these temporary code changes is the root of the problem. Can SDA really be controlled, or is something else masking the problem.

inout testbench

hi,

I tried it but nothing has happened. I mean that the SDA has a constant z value, no matter if

assign SDA = (OE == 1) ? SDA_reg : 1'b0;

OR

assign SDA = (OE == 1) ? SDA_reg : 1'b1;

I have already tried to define SDA_reg as tri and trireg but it was useless...

verilog testbench inout

I've faced the same problem by using bidirectional like Kirvan is doing. Let's do some logical stuff :
(1) Inout port is bidirectional port, means it's an input port with some part of your design but also the output port of some other part of your design, and you cant assign any value for the design output port, because their values are directly computed from the value of other input port.
Let say a very simple but examplary example, a full adder, in structural modeling. All of us know that the full adder can be archieved by concat 2 half adder, the output signal of the 1st half adder is also the input of the second half adder, however we can't assign any value for this intermediate(inout port) , because its value is driven by 2 global inputs, say a and b.
With ur case, u have to defined the global inputs(one dimension only) and give the value to it, but not the bidiectional one....

open drain verilog

Atena,

sorry but I'm not sure that I understand you correctly. So, do you mean that [in the module] SDA and SCL should be input and...

atena said:

...give the value to it, but not the bidiectional one....

Click to expand...

This is what I don't understand. Can you explain it, please? You know, the SDA has to be an inout according to the i2c protocol...

verilog inout port reg

Since SDA is stuck at 'z', it seems like either a testbench port problem or the entire design is stuck in reset.
Which level of the design are you displaying SDA at? Are you displaying the testbench signal or the one down inside your actual logic. I would push down into the logic and display SDA, SDA_reg, and OE. If these are normal at the lower level, then its a hookup problem in the testbench. If they are bad at the lower level, then the logic is stuck in reset, or does not see a clock or something similar.

Are you sure you included everything that the logic needs to simulate? For example, with Xilinx, you often have to include glbl.v . This file contains "stuff" that gets the design out of reset. Older designs used to have to include a startup file or startup block.

Please do not get hung up on the inout part. To prove whether inout is the root of the problem, change the SDA to output only and see if the 'z' becomes a good logic level.

verilog driving inout

I mean to say that you'd better break your design into a number of submodules. Each submodule contains only input and output ports, no inout port. The inout port is nothing but the wire to connect each submodule only ... From my opinion it's the best way to avoid any problem with the HDL design...

inout port

Hi krivan, Can you show us a complete module that demonstrates the problem? That would help the discussion.

inouts in testbench

Hi all,

Banjo:
everything[SDA_reg, SCL,...] seems to work except the SDA. The SDA is stuck in 'z' and so I can't give the input to the module I call i2c_slave_code3.
Well...I hope that I have everything for the simulation. I am new to ModelSim[I work with ModelSim] and I haven't heared about such file glbl.v yet. I will check...
I tried to set SDA to "output" but the problem is the same.

Atena:
Ah, ok. I will try it, thank you. Is the "inout" really just a "wire" which connects an "input" and an "output"? I mean, is the synthesized element really just a wire between a inout and an output submodules?

echo47:
yes, you're right. Here is the code of the testbench.

Thank you for your help.




module test_i2c_slave_code();

wire SDA;

reg SDA_reg;
reg SCL;
reg P1, P2;
reg OE = 1;

reg start;


i2c_slave_code3 u(SCL,
SDA,
P1,
P2
);

assign SDA = (OE == 1) ? SDA_reg : 1'bz;

initial
begin
start = 0;
SDA_reg = 1;
SCL = 0;
P1 = 0;
P2 = 1;
#10
SDA_reg = 0;
start = 1;
#1
SDA_reg = 1;
#1
SDA_reg = 0;
#1
SDA_reg = 1;
#1
SDA_reg = 1;
#1
SDA_reg = 0;
#1
SDA_reg = 0;
#1
SDA_reg = 1;
#1
SDA_reg = 1;
#1
SDA_reg = 0;
#1
SDA_reg = 1;
#1
SDA_reg = 1;
#1
SDA_reg = 0;
#1
SDA_reg = 0;
#1
SDA_reg = 0;
#1
SDA_reg = 1;
$display("x. bit");
end

initial
begin
@(posedge start)
forever #1 SCL = !SCL;
end
endmodule

test bench in verilog

Using ModelSim SE 6.3e, I don't see the perpetual 'z' state you described.

I had to comment-out the i2c_slave_code3 instantiation because I don't have that module. Maybe that module contains a problem?

i2c verilog testbench

Hmmm...strage. I tried it without the i2c module[commented] and I get the same result as you...ehhh.

In the i2c module the SDA is an inout which is assigned to sda_R [this is a reg] as follows

assign SDA = (OE == 1) ? sda_R : 1'bz;

where

reg OE = 1;

I read/write the sda_R to/from a command register.
Is perhaps this reg - inout assign wrong?

/krivan

verilog testbench inout port

Since it does work with the lower level commented out, I think you have some sort of bus contention or lack of a pullup. The I2C data line is an open drain system. Do you have a pullup to a logic one in the testbench? If not, then perhaps the lower level is attempting to output a '1' which means it just releases the line. However, with no pullup, the line appears to go high Z.

trireg testbench

It would be helpful to see all the source code, if it's not confidential.

In your simulator display, be sure you aren't confusing the floating 'z' state with the unknown 'x' state. Signal contention (two drivers fighting with each other) can result in an 'x' state.

By the way, your test bench is not simulating the open-drain nature of I2C. It's driving SDA both high and low, but it should only be driving it low. Use a continuous weak pullup to keep the signal high when it's not being driven low.

Re: verilog driving inout

atena said:

I mean to say that you'd better break your design into a number of submodules. Each submodule contains only input and output ports, no inout port. The inout port is nothing but the wire to connect each submodule only ... From my opinion it's the best way to avoid any problem with the HDL design...

Click to expand...

atena's right, you should break your design into submodules. For example,

in module 1, you can set SDA as input and in module 2, set SDA as output. Then finally, in your top module, set SDA as a wire. No need to define SDA as an inout port.

I have had this problem once. Hope it helps