godis_knugen
Newbie level 4
verilog include
is there an easy way to put a design in vhdl inside a verilog design?
i have a nice dynamic verilog file with port declarations towards the external hw, but i want to write my own logic in vhdl. not so familiar with verilog yet.
can i write some kind of wrapper for the vhdl? if so, how?
is there an easy way to put a design in vhdl inside a verilog design?
i have a nice dynamic verilog file with port declarations towards the external hw, but i want to write my own logic in vhdl. not so familiar with verilog yet.
can i write some kind of wrapper for the vhdl? if so, how?