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question about rail to rail input/output amp

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stephenho

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Could you please tell my how to set DC voltage level of drain of M16 and M14?

This is a rail to rail input and output amplifier and its constant-gm control circuit is omitted.
M25 and M26 are class-AB output transistors.Threshold voltage are -0.65V and 0.73V, respectively.And VDD is 3V.

So,my question are:
(1) what is exact DC voltage for the drain of M16 and M14?
(2)if DC voltage of the drain of M16 and M14 are already made certain,how to set DC voltage level of drain of M16 and M14?

Thank you all, wish you good luck.This is the first quesiton of mine.
 

What I understand form the schematic
is that the M14 and M16 are the cascode devices.
These two are driving the class A-B output so ..

.. at Max VDRAIN(M14) = VDD - | Vtp |
.. and Min VDRAIN(M16) = Vtn

Other limits will be according to swing specs , i suppose ..

Regards
Raduga
 

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    stephenho

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M11-M18 compose the cascade current mirror load. According to the type of the cascade current mirror:
The maximum drain voltage of M14 is VDD-2*VODp, where, VODp is the over drive voltage of PMOS.
And the mimimum drain voltage of M16 is 2*VODn, where, VODn is the over drive voltage of NMOS.

The actual drain voltage of M14 and M16 is determined by the bias current and the size of M19 and M20. The drain voltages of M14 and M16 should be separated enough to ensure that M25 and M26 do not conduct simutaneously when no input signal.
 

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    stephenho

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I have implemented this circuit(I mean Class-AB outout stage and summing circuit).
M19 and M20,the mesh transistors,compose a "floating voltage source".
Voltage difference between M19's source and M20's source is 1.137V in my circuit and quiescent currents flow through M19 and M20 are 7.5uA.

But, when a small voltage signal is applied on gates of complementary input transistors, there is still voltage sine vibration between M19's source and M20's source,and magnitude is about 1mV.

If anyone knows something about this circuit,PLZ tell me.I appriate the help.
 

But why do you wonder from this? There are must be a voltage variation bw sources M19 and M20. This voltage variation is Uinp*Gm*[1/(gm19+gm20)], here Uinp - input voltage on gates of complementary input transistors, Gm - transcondactance of the input complementary differential pair, gmn - transcondactance of each M19 and M20.
 

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    stephenho

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in which ic number rail to rail operation avilable
 

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    stephenho

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