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What precautions can we take to make layout compatible with DFM?

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WHat precautions can we take as analog layout engineer to make layout compatible with DFM?

I have not used DFM based tools..plz tell How do we test whether our layot is compatible with DFM or not ?
Thnx
 

Re: DFM issue ?

It depends what technology you are working with. Typically geometries below 0.13u DFM would perhaps be an issue, although don't quote me on it. The smallest tech I've worked in is 0.18u which didn't have this issue.

DRM rules follow rules such as double vias and focus more on crosstalk and stp issues.
The FAB would supply a set of design rules to design by.
I think companies like cadence supply tools for checking and laying out for DFM.
 
DFM issue ?

What is the process you working at?
From 130nm and below to nano world, DFM is getting increasinly more.

Its not really a design rules but more as a guidelines which we could fix it oppurtunistically to help improved the circuitry performances, yield, reliability, variation , and many more.

When you reached 65nm and below, more and more of this guidelines will eventually become DRC as it is getting really serious.

You may want to check with you foundry if they do provide you such verification (run-sets) of DFM.
 
DFM issue ?

the foundry should provide the DFM rule, as a design engineer, we only need to follow it.
 
Re: DFM issue ?

Hi,
You have to use DFM(Design for Manufacturability) guide lines in Layout to reduce the chances of occurances of faults (shorts) and to improve YIELD without increasing the area of the layout.

Ex: Redundant contacts, redundant vias, more poly overhang, extra spacing b/w L-shaped poly & diff, extra space b/w L-shaped diff & poly etc

You can run DFM rule file separately after DRC run.
 
Re: DFM issue ?

Regards,
I'm working about DFM methodologies. It commonly defines two types of yielding's losses.
i) Functional Losses due to defects on layout geometry like spots, pinholes, etc.
ii)Parametric losses due to variability in nominal values of components and mismatch between them. Normally it cause losses in performance of the cell or circuit.

To overcome the problems report above, u must be sure to put into the layout the layers in common centroid, and also to try increase W*L. The later due to Pelgrom's Model that defines the mismatch as:
sigma(delta(P))=A_p/(sqrt(WL)) (1)
I recommend the following file , available in EDABOARD too:
 

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