sameem_shabbir
Advanced Member level 4
verilog instantiation
Hi all
I am a verilog user , I am facing problems in instantaiting verilog module into VHDL
Below is the instantiation which i did
CPU: Calc PORT MAP(
eof => eof,
blank => blank,
clk1x => clk,
r => r,
rmd => rmd,
mlpl => mlpl,
sqr => sqr,
quo => quo
);
But the compiler is giving syntax error
Undefined symbol 'Calc'.
Where as Calc.v is the verilog file which i am trying to instantiate
can any body help me how to correct this error
Hi all
I am a verilog user , I am facing problems in instantaiting verilog module into VHDL
Below is the instantiation which i did
CPU: Calc PORT MAP(
eof => eof,
blank => blank,
clk1x => clk,
r => r,
rmd => rmd,
mlpl => mlpl,
sqr => sqr,
quo => quo
);
But the compiler is giving syntax error
Undefined symbol 'Calc'.
Where as Calc.v is the verilog file which i am trying to instantiate
can any body help me how to correct this error