Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
due to channel lenght modulation there is no channel at the drain side of MOS when it is biased in deep saturation region, so the overlap capacitance between gate and drain get added with oxide capacitance bcoz under gate oxide surface at drain end there is a depletion region which act as insulator and over all capacitance included gate drain overlap capacitance.
An easy way to think about it is that now you have one plate (your gate), you have dielectric (SiO2) but your bottom plate (channel) is missing at drain side due to channel length modulation. That's why your Cgd now is nearly zero.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
