kishore2k4
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I am trying to design a direct-down conversion RF receiver to decode 64-QAM 256-OFDM signals. The input frequency range is 600MHz-1000Mhz. I am planning to use the following signal chain
Antenna->LNA(ADL5521)->Quadrature Demodulator(AD8348)->Low Pass Filter (2Mhz)-> 12-bit Dual Channel ADC(>20MSPS)-> FPGA
The LNA has a Noise Figure of 0.8dB (typ) and the I/Q demodulator has a Noise Figure of 11dB (typical).
My question is: Is the above design a good one, as in high receiver sensitivity for 2Mhz channel bandwidths? My previous thread regarding Zero-IF conversion lead to suggesting that I stick with IF-Sampling but size is also an important factor for my design. Will a IF-Sampling (Single or Double Conversion) design yield better results?
I didn't use any differential buffers to drive the ADC because the Quadrature Demodulator(AD8348) has basedband amplifiers built-in that can directly drive an ADC.
Feel free to suggest changes or entirely different designs as I have never designed RF related circuits before. Thanks.
Antenna->LNA(ADL5521)->Quadrature Demodulator(AD8348)->Low Pass Filter (2Mhz)-> 12-bit Dual Channel ADC(>20MSPS)-> FPGA
The LNA has a Noise Figure of 0.8dB (typ) and the I/Q demodulator has a Noise Figure of 11dB (typical).
My question is: Is the above design a good one, as in high receiver sensitivity for 2Mhz channel bandwidths? My previous thread regarding Zero-IF conversion lead to suggesting that I stick with IF-Sampling but size is also an important factor for my design. Will a IF-Sampling (Single or Double Conversion) design yield better results?
I didn't use any differential buffers to drive the ADC because the Quadrature Demodulator(AD8348) has basedband amplifiers built-in that can directly drive an ADC.
Feel free to suggest changes or entirely different designs as I have never designed RF related circuits before. Thanks.