xtcx
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Hi everybody!, consider this example,
PROCESS(clk)IS
VARIABLE a,b,c : STD_LOGIC;
BEGIN
IF RISING_EDGE(Clk) THEN
a:= '1';
b:= NOT(a);
c:= a OR b;
END IF;
END PROCESS;
The above statements should be executed in sequence,since the declaration type is a variable. How much time\clock cylces does it take for the successive statements to be executed one after another?...Is it the internal latency of the flipflop?.
PROCESS(clk)IS
VARIABLE a,b,c : STD_LOGIC;
BEGIN
IF RISING_EDGE(Clk) THEN
a:= '1';
b:= NOT(a);
c:= a OR b;
END IF;
END PROCESS;
The above statements should be executed in sequence,since the declaration type is a variable. How much time\clock cylces does it take for the successive statements to be executed one after another?...Is it the internal latency of the flipflop?.